A 1.2 V 1.5 Gb/s 72 Mb DDR3 SRAM

Abstract

A 1.2 V 72 Mb DDR3 SRAM in a 0.10 /spl mu/m CMOS process achieves a data rate of 1.5 Gb/s using dynamic self-resetting circuits. Single-ended main data lines reduce the power dissipation and the number of data lines by half. Clocks phase-shifted by 0/spl deg/, 90/spl deg/ and 270/spl deg/ are generated by clock adjustment circuits. On-chip input termination with linearity of /spl plusmn/4.1% is developed to improve signal integrity at higher data rates.