Zongjian Chen, D. Murray, S. Nishimoto, M. Pearce, M. Oyker, D. Rodriguez, R. Rogenmoser, Dongwook Suh, E. Supnet, V. V. Kaenel, G. Yiu
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A 2/spl times/ load/store pipe for a low-power 1GHz embedded processor
The load/store pipe in an embedded processor is clocked at 2/spl times/ the processor clock frequency. It sustains two load or store operations per core clock cycle with zero load-to-use issue latency. The design is implemented in 0.13/spl mu/m 7M CMOS process and dissipates between 650 and 1090mW for core clock frequencies between 600MHz and 1GHz.
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