一个1.8 V 128 Mb 125 MHz多级单元闪存具有灵活的读同时写

2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. Pub Date : 2003-10-27 DOI:10.1109/ISSCC.2003.1234304

D. Elmhurst, R. Bains, T. Bressie, C. Bueb, E. Carrieri, B. Chauhan, N. Chrisman, M. Dayley, R. De Luna, K. Fan, M. Goldman, P. Govindu, A. Huq, M. Khandaker, J. Kreifels, S. Krishnamachari, P. Lavapie, K. Loe, T. Ly, F. Marvin, R. Melcher, S. Monasa, Q. Nguyen, B. Pathak, A. Proescholdt, T. Rahman, B. Srinivasan, R. Sundaram, P. Walimbe, D. Ward, D. Zeng, H. Zhang

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引用次数: 22

摘要

采用0.13 /spl mu/m技术的每单元2位设计的128mb闪存可实现55 ns的随机访问时间和125 MHz的同步操作。该设计结合了灵活的多分区存储器架构，允许程序或擦除操作发生在存储器的一个分区中，而将数据从另一个分区中取出。模具尺寸为27.3 mm/sup 2/，单元尺寸为0.154 /spl mu/m/sup 2/。

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A 1.8 V 128 Mb 125 MHz multi-level cell flash memory with flexible read while write

A 128 Mb flash memory with a two bit-per-cell design on a 0.13 /spl mu/m technology achieves a random access time of 55 ns and 125 MHz synchronous operation. The design incorporates a flexible multi-partition memory architecture which allows a program or erase operation to occur in one partition of the memory while bursting data out of another partition. The die is 27.3 mm/sup 2/ with a 0.154 /spl mu/m/sup 2/ cell size.

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来源期刊

2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.

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