A 2.5-10Gb/s CMOS transceiver with alternating edge sampling phase detection for loop characteristic stabilization

Abstract

A 2.5 to 10 Gb/s CMOS transceiver in 0.18 /spl mu/m CMOS dissipates 540 mW from a 1.8 V supply with a BER better than 10/sup -12/. CDR loop characteristics are stabilized across various jitter environments with small hardware overhead using an alternating edge sampling phase detector.