1.2 V 1.5 Gb/s 72 Mb DDR3 SRAM

2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. Pub Date : 2003-10-27 DOI:10.1109/JSSC.2003.818137

Uk-Rae Cho, Tae-Hyoung Kim, Yong-Jin Yoon, Jong-Cheol Lee, Dae-Gi Bae, Nam-Seog Kim, Kang-Young Kim, Young-Jae Son, Jeonghyu Yang, Kwon-Il Sohn, Sung-Tae Kim, I. Lee, Kwang-Jin Lee, Tae-Gyoung Kang, Su-Chul Kim, Kee-Sik Ahn, H. Byun

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引用次数: 12

摘要

1.2 V 72mb DDR3 SRAM采用0.10 /spl mu/m CMOS工艺，采用动态自复位电路实现1.5 Gb/s的数据速率。采用单端主数据线，功耗和数据线数减少一半。由时钟调整电路产生相移0/spl度、90/spl度和270/spl度的时钟。开发了线性度为/spl plusmn/4.1%的片上输入端，以提高更高数据速率下的信号完整性。

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A 1.2 V 1.5 Gb/s 72 Mb DDR3 SRAM

A 1.2 V 72 Mb DDR3 SRAM in a 0.10 /spl mu/m CMOS process achieves a data rate of 1.5 Gb/s using dynamic self-resetting circuits. Single-ended main data lines reduce the power dissipation and the number of data lines by half. Clocks phase-shifted by 0/spl deg/, 90/spl deg/ and 270/spl deg/ are generated by clock adjustment circuits. On-chip input termination with linearity of /spl plusmn/4.1% is developed to improve signal integrity at higher data rates.

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来源期刊

2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.

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