K. Yoshida, O. Tsuchiya, Y. Yamaguchi, J. Kishimoto, Y. Ikeda, S. Narumi, Y. Takase, K. Furusawa, K. Izawa, T. Yoshitake, T. Kobayashi, H. Kurata, M. Kanemitsu
{"title":"A 1 Gb multilevel AG-AND-type flash memory with 10 MB/s programming throughput for mass storage application","authors":"K. Yoshida, O. Tsuchiya, Y. Yamaguchi, J. Kishimoto, Y. Ikeda, S. Narumi, Y. Takase, K. Furusawa, K. Izawa, T. Yoshitake, T. Kobayashi, H. Kurata, M. Kanemitsu","doi":"10.1109/ISSCC.2003.1234305","DOIUrl":null,"url":null,"abstract":"A 1 Gb multilevel flash memory is fabricated in a 0.13 /spl mu/m CMOS process. The chip area of 95 mm/sup 2/ is achieved using AG-AND-type cells with a multilevel program cell technique and compact write-buffer. By use of constant-charge-injection programming and multi-bank operation, high-speed programming throughput of 10 MB/s achieved.","PeriodicalId":171288,"journal":{"name":"2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.","volume":"17 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-02-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2003.1234305","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 9
Abstract
A 1 Gb multilevel flash memory is fabricated in a 0.13 /spl mu/m CMOS process. The chip area of 95 mm/sup 2/ is achieved using AG-AND-type cells with a multilevel program cell technique and compact write-buffer. By use of constant-charge-injection programming and multi-bank operation, high-speed programming throughput of 10 MB/s achieved.