{"title":"可变核闪存卷积图像滤波处理器","authors":"K. Ito, M. Ogawa, T. Shibata","doi":"10.1109/ISSCC.2003.1234391","DOIUrl":null,"url":null,"abstract":"A VLSI image filtering processor is designed for single-clock-cycle kernel convolution employing quaternary-tile pixel-data mapping and variable data masking techniques. The concept has been verified by a test chip fabricated in 0.18/spl mu/m CMOS 5M technology. Without pipelining the IC operates at 50MHz with a 1.8V supply.","PeriodicalId":171288,"journal":{"name":"2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.","volume":"29 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-02-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"A variable-kernel flash-convolution image filtering processor\",\"authors\":\"K. Ito, M. Ogawa, T. Shibata\",\"doi\":\"10.1109/ISSCC.2003.1234391\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A VLSI image filtering processor is designed for single-clock-cycle kernel convolution employing quaternary-tile pixel-data mapping and variable data masking techniques. The concept has been verified by a test chip fabricated in 0.18/spl mu/m CMOS 5M technology. Without pipelining the IC operates at 50MHz with a 1.8V supply.\",\"PeriodicalId\":171288,\"journal\":{\"name\":\"2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.\",\"volume\":\"29 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2003-02-09\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.2003.1234391\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2003.1234391","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A variable-kernel flash-convolution image filtering processor
A VLSI image filtering processor is designed for single-clock-cycle kernel convolution employing quaternary-tile pixel-data mapping and variable data masking techniques. The concept has been verified by a test chip fabricated in 0.18/spl mu/m CMOS 5M technology. Without pipelining the IC operates at 50MHz with a 1.8V supply.