使用耦合驻波振荡器的10GHz时钟分布

2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. Pub Date : 2003-02-09 DOI:10.1109/ISSCC.2003.1234369

F. O’Mahony, C. Yue, M. Horowitz, S.S. Wong

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引用次数: 41

摘要

一个由耦合驻波振荡器组成的全球时钟网络在0.18/spl mu/m 6M CMOS工艺中原型化。时钟网络工作在9.8到10.5 GHz之间，偏差为0.6ps，当参考rms抖动为1.4ps的时钟源时，仅贡献0.5ps的抖动。

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10GHz clock distribution using coupled standing-wave oscillators

A global clock network comprised of coupled, standing-wave oscillators is prototyped in a 0.18/spl mu/m 6M CMOS process. The clock network operates from 9.8 to 10.5 GHz with 0.6ps skew and contributes only 0.5ps jitter when referencing a clock source with 1.4ps rms jitter.

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来源期刊

2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.

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