A variable-kernel flash-convolution image filtering processor

2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. Pub Date : 2003-02-09 DOI:10.1109/ISSCC.2003.1234391

K. Ito, M. Ogawa, T. Shibata

引用次数: 9

Abstract

A VLSI image filtering processor is designed for single-clock-cycle kernel convolution employing quaternary-tile pixel-data mapping and variable data masking techniques. The concept has been verified by a test chip fabricated in 0.18/spl mu/m CMOS 5M technology. Without pipelining the IC operates at 50MHz with a 1.8V supply.

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可变核闪存卷积图像滤波处理器

采用四元像素数据映射和可变数据掩蔽技术，设计了一种用于单时钟周期核卷积的超大规模集成电路图像滤波处理器。该概念已通过0.18/spl mu/m CMOS 5M技术制造的测试芯片进行验证。没有流水线IC工作在50MHz 1.8V电源。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.

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