发布求助
文献互助 智能选刊 最新文献

2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.最新文献

筛选
英文 中文
A 750MHz 144Mb cache DRAM LSI with speed scalable design and programmable at-speed function-array BIST 一个750MHz 144Mb高速缓存DRAM LSI，具有高速可扩展设计和可编程的高速功能阵列BIST
2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. Pub Date : 2003-02-09 DOI: 10.1109/ISSCC.2003.1234385
H. Sakakibara, M. Nakayama, M. Kusunoki, K. Kurita, H. Otori, M. Hasegawa, S. Iwahashi, K. Higeta, T. Hanashima, H. Hayashi, K. Kuchimachi, K. Uehara, T. Nishiyama, M. Kume, K. Miyamoto, E. Kamada
{"title":"A 750MHz 144Mb cache DRAM LSI with speed scalable design and programmable at-speed function-array BIST","authors":"H. Sakakibara, M. Nakayama, M. Kusunoki, K. Kurita, H. Otori, M. Hasegawa, S. Iwahashi, K. Higeta, T. Hanashima, H. Hayashi, K. Kuchimachi, K. Uehara, T. Nishiyama, M. Kume, K. Miyamoto, E. Kamada","doi":"10.1109/ISSCC.2003.1234385","DOIUrl":"https://doi.org/10.1109/ISSCC.2003.1234385","url":null,"abstract":"A 750MHz 144Mb cache DRAM LSI incorporates speed-scalable embedded DRAM and SRAM macros, and is realized using a logic-merged DRAM process. The LSI has a built-in at-speed test engine with programmable test pattern and timing, merging logic and memory test. The die area is 285mm/sup 2/ in a 0.18/spl mu/m 6M logic-merged DRAM process.","PeriodicalId":171288,"journal":{"name":"2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-02-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131527601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A 1.6Gb/s/pair electromagnetically coupled multidrop bus using modulated signaling 使用调制信号的1.6Gb/s/对电磁耦合多路总线
2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. Pub Date : 2003-02-09 DOI: 10.1109/ISSCC.2003.1234259
T. Simon, R. Amirtharajah, J. R. Benham, J. Critchlow, T. Knight
{"title":"A 1.6Gb/s/pair electromagnetically coupled multidrop bus using modulated signaling","authors":"T. Simon, R. Amirtharajah, J. R. Benham, J. Critchlow, T. Knight","doi":"10.1109/ISSCC.2003.1234259","DOIUrl":"https://doi.org/10.1109/ISSCC.2003.1234259","url":null,"abstract":"AC coupling and pulse modulation are presented for high speed multidrop busses. A prototype eight module memory bus operates at a 400MHz symbol rate with 4 bits of modulated data per symbol, for 1.6Gb/s/pair. Test chips in 0.25/spl mu/m 3M CMOS dissipate 40mW peak and occupy 340/spl times/200/spl mu/m per pair.","PeriodicalId":171288,"journal":{"name":"2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-02-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130914730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A low-jitter and precise multiphase delay-locked loop using shifted averaging VCDL 利用移位平均VCDL的低抖动精确多相锁滞环
2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. Pub Date : 2003-02-09 DOI: 10.1109/ISSCC.2003.1234373
Hsiang-Hui Chang, C. Sun, Shen-Iuan Liu
{"title":"A low-jitter and precise multiphase delay-locked loop using shifted averaging VCDL","authors":"Hsiang-Hui Chang, C. Sun, Shen-Iuan Liu","doi":"10.1109/ISSCC.2003.1234373","DOIUrl":"https://doi.org/10.1109/ISSCC.2003.1234373","url":null,"abstract":"The DLL, in 0.35/spl mu/m CMOS, uses the shifted averaging VCDL to reduce the mismatch-induced timing error among the delay stages without extra hardware. The DLL can generate precise multiphase outputs with improved duty cycle, reduced skew errors, and lowered jitter. Compared with a conventional DLL, this design improves the peak-to-peak jitter by a factor of 1.4 at 150MHz.","PeriodicalId":171288,"journal":{"name":"2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-02-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128284680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 36
A 1.8 V 2 Gb NAND flash memory for mass storage applications 1.8 V 2gb NAND快闪记忆体，适用于大容量储存应用
2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. Pub Date : 2003-02-09 DOI: 10.1109/ISSCC.2003.1234306
June Lee, Sungsoo Lee, O. Kwon, Kyeong-Han Lee, Kyongjoo Lee, D. Byeon, In-young Kim, Y. Lim, Byung-Soon Choi, Jong-Sik Lee, W. Shin, Jeong-Hyuk Choi, K. Suh
{"title":"A 1.8 V 2 Gb NAND flash memory for mass storage applications","authors":"June Lee, Sungsoo Lee, O. Kwon, Kyeong-Han Lee, Kyongjoo Lee, D. Byeon, In-young Kim, Y. Lim, Byung-Soon Choi, Jong-Sik Lee, W. Shin, Jeong-Hyuk Choi, K. Suh","doi":"10.1109/ISSCC.2003.1234306","DOIUrl":"https://doi.org/10.1109/ISSCC.2003.1234306","url":null,"abstract":"A 1.8 V 2 Gb NAND flash memory is fabricated in a 90 nm process resulting in a 141 mm/sup 2/ die and a 0.044 /spl mu/m/sup 2/ effective cell. To achieve the high level of integration, critical layers are patterned with KF photolithography and phase-shift masks with proximity correction.","PeriodicalId":171288,"journal":{"name":"2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-02-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126530782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Low-noise monolithic oscillator with an integrated three-dimensional inductor 具有集成三维电感的低噪声单片振荡器
2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. Pub Date : 2003-02-09 DOI: 10.1109/ISSCC.2003.1234351
K. Van Schuylenbergh, B. Griffiths, C. Chua, D. Fork, J. Lu
{"title":"Low-noise monolithic oscillator with an integrated three-dimensional inductor","authors":"K. Van Schuylenbergh, B. Griffiths, C. Chua, D. Fork, J. Lu","doi":"10.1109/ISSCC.2003.1234351","DOIUrl":"https://doi.org/10.1109/ISSCC.2003.1234351","url":null,"abstract":"A balanced silicon BiCMOS oscillator using self-assembled curled circular spring 3D inductor with peak Q of 40 reduces phase noise by 12.3dB at 100kHz offset compared to conventional planar spiral inductor approach. The addition of a 5/spl mu/m copper underlayer raises Q to 85.","PeriodicalId":171288,"journal":{"name":"2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-02-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126583429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Strained SOI technology for high-performance, low-power CMOS applications 用于高性能、低功耗CMOS应用的应变SOI技术
2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. Pub Date : 2003-02-09 DOI: 10.1109/ISSCC.2003.1234343
S. Takagi, T. Mizuno, T. Tezuka, N. Sugiyama, T. Numata, K. Usuda, Y. Moriyama, S. Nakaharai, J. Koga, A. Tanabe, T. Maeda
{"title":"Strained SOI technology for high-performance, low-power CMOS applications","authors":"S. Takagi, T. Mizuno, T. Tezuka, N. Sugiyama, T. Numata, K. Usuda, Y. Moriyama, S. Nakaharai, J. Koga, A. Tanabe, T. Maeda","doi":"10.1109/ISSCC.2003.1234343","DOIUrl":"https://doi.org/10.1109/ISSCC.2003.1234343","url":null,"abstract":"Advantages of strained-SOI CMOS and the impact on circuit performance are presented from the viewpoint of ring oscillator speed, floating body effects, threshold voltage control and gate leakage reduction. Circuit performance enhancement of about 1.7 times over conventional SOI CMOS is verified experimentally at 0.95/spl mu/m gate lengths and theoretically expected even at gate lengths of 50nm.","PeriodicalId":171288,"journal":{"name":"2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-02-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114644000","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 1 GOPS reconfigurable signal processing IC with embedded FPGA and 3-port 1.2 GB/s flash memory subsystem 1 GOPS可重构信号处理集成电路，内置FPGA和3端口1.2 GB/s闪存子系统
2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. Pub Date : 2003-02-09 DOI: 10.1109/ISSCC.2003.1234203
M. Borgatti, L. Call, G. De Sandre, B. Forêt, D. Iezzi, F. Lertora, G. Muzzi, M. Pasotti, M. Poles, P. Rolandi
{"title":"A 1 GOPS reconfigurable signal processing IC with embedded FPGA and 3-port 1.2 GB/s flash memory subsystem","authors":"M. Borgatti, L. Call, G. De Sandre, B. Forêt, D. Iezzi, F. Lertora, G. Muzzi, M. Pasotti, M. Poles, P. Rolandi","doi":"10.1109/ISSCC.2003.1234203","DOIUrl":"https://doi.org/10.1109/ISSCC.2003.1234203","url":null,"abstract":"A 1 GOPS dynamically reconfigurable processing unit with embedded flash memory and SRAM-based FPGA for image/voice processing/recognition applications is described. Code, data and FPGA bitstreams are stored in the embedded flash memory and are independently accessible through 3 content-specific, 64 b I/O ports with a peak read rate of 1.2 GB/s. The system is implemented in a 0.18 /spl mu/m 2P 6M CMOS flash technology with a chip area of 70 mm/sup 2/.","PeriodicalId":171288,"journal":{"name":"2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.","volume":"276 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-02-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124263760","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Powder LSI: an ultra small RF identification chip for individual recognition applications 粉末LSI:一种用于个人识别应用的超小型射频识别芯片
2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. Pub Date : 2003-02-09 DOI: 10.1109/ISSCC.2003.1234354
M. Usami, A. Sato, K. Sameshima, K. Watanabe, H. Yoshigi, R. Imura
{"title":"Powder LSI: an ultra small RF identification chip for individual recognition applications","authors":"M. Usami, A. Sato, K. Sameshima, K. Watanabe, H. Yoshigi, R. Imura","doi":"10.1109/ISSCC.2003.1234354","DOIUrl":"https://doi.org/10.1109/ISSCC.2003.1234354","url":null,"abstract":"A powder-like 0.09 mm/sup 2/ 2.45 GHz RF identification chip for wireless recognition applications is described. This chip is fabricated in a 0.18 /spl mu/m CMOS process, and its thickness is 60 /spl mu/m. A two-surface connection technique is adopted to facilitate antenna attachment. The distance between the chip and a reader is 300 mm for a reader power of 300 mW.","PeriodicalId":171288,"journal":{"name":"2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-02-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117168040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 68
Impact of dielectric relaxation on a 14 b pipeline ADC in 3 V SiGe BiCMOS 介电弛豫对3v SiGe BiCMOS中14b管路ADC的影响
2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. Pub Date : 2003-02-09 DOI: 10.1109/ISSCC.2003.1234321
A. Zanchi, F. Tsay, I. Papantonopoulos
{"title":"Impact of dielectric relaxation on a 14 b pipeline ADC in 3 V SiGe BiCMOS","authors":"A. Zanchi, F. Tsay, I. Papantonopoulos","doi":"10.1109/ISSCC.2003.1234321","DOIUrl":"https://doi.org/10.1109/ISSCC.2003.1234321","url":null,"abstract":"Dielectric relaxation in PECVD SiN capacitors of a 45 GHz 0.4 /spl mu/m SiGe BiCMOS process degrades performance even at low frequencies. In the design of pipelined 14 b 70 MS/s ADC, the effects of dielectric relaxation are identified via behavioral/circuit simulations and ad-hoc tests. After LPCVD oxide capacitors are introduced, a 5.3/spl times/5.3 mm/sup 2/ test chip delivers 72 dB SNR, 81 dBc SFDR, and 11.5 ENOB at 70 MS/s with a 1 MHz input. The IC dissipates 1 W from 3.3 V.","PeriodicalId":171288,"journal":{"name":"2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-02-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129711914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 0.5V, 400MHz, V/sub 00/-hopping processor with zero-V/sub TH/ FD-SOI technology 0.5V, 400MHz, V/sub - 00/跳频处理器，采用零V/sub - TH/ FD-SOI技术
2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. Pub Date : 2003-02-09 DOI: 10.1109/ISSCC.2003.1234227
H. Kawaguchi, K. Kanda, K. Nose, S. Hattori, D. Dwi, D. Antono, D. Yamada, T. Miyazaki, K. Inagaki, T. Hiramoto, T. Sakurai
{"title":"A 0.5V, 400MHz, V/sub 00/-hopping processor with zero-V/sub TH/ FD-SOI technology","authors":"H. Kawaguchi, K. Kanda, K. Nose, S. Hattori, D. Dwi, D. Antono, D. Yamada, T. Miyazaki, K. Inagaki, T. Hiramoto, T. Sakurai","doi":"10.1109/ISSCC.2003.1234227","DOIUrl":"https://doi.org/10.1109/ISSCC.2003.1234227","url":null,"abstract":"A 0.5V, 400MHz, 3.5mW, 16b RISC processor with a 0.25/spl mu/m, dual V/sub T/, fully-depleted SOI technology is presented. Zero V/sub T/ is used in logic for high speed while memories and register files adopt a higher V/sub 00/ and V/sub T/ to suppress leakage. Experimental results show that V/sub 00/-hopping is effective in leakage dominant environments.","PeriodicalId":171288,"journal":{"name":"2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-02-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128628415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信