介电弛豫对3v SiGe BiCMOS中14b管路ADC的影响

2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. Pub Date : 2003-02-09 DOI:10.1109/ISSCC.2003.1234321

A. Zanchi, F. Tsay, I. Papantonopoulos

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引用次数: 6

摘要

45 GHz 0.4 /spl mu/m SiGe BiCMOS工艺的PECVD SiN电容器的介电弛豫即使在低频下也会降低性能。在流水线式14 b 70 MS/s ADC的设计中，通过行为/电路模拟和临时测试确定了介电弛豫的影响。在引入LPCVD氧化物电容器后，一个5.3/spl倍/5.3 mm/sup /的测试芯片在70 MS/s、1 MHz输入下提供72 dB信噪比、81 dBc SFDR和11.5 ENOB。IC在3.3 V时的功耗为1w。

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Impact of dielectric relaxation on a 14 b pipeline ADC in 3 V SiGe BiCMOS

Dielectric relaxation in PECVD SiN capacitors of a 45 GHz 0.4 /spl mu/m SiGe BiCMOS process degrades performance even at low frequencies. In the design of pipelined 14 b 70 MS/s ADC, the effects of dielectric relaxation are identified via behavioral/circuit simulations and ad-hoc tests. After LPCVD oxide capacitors are introduced, a 5.3/spl times/5.3 mm/sup 2/ test chip delivers 72 dB SNR, 81 dBc SFDR, and 11.5 ENOB at 70 MS/s with a 1 MHz input. The IC dissipates 1 W from 3.3 V.

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来源期刊

2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.

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