1 GOPS可重构信号处理集成电路，内置FPGA和3端口1.2 GB/s闪存子系统

2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. Pub Date : 2003-02-09 DOI:10.1109/ISSCC.2003.1234203

M. Borgatti, L. Call, G. De Sandre, B. Forêt, D. Iezzi, F. Lertora, G. Muzzi, M. Pasotti, M. Poles, P. Rolandi

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引用次数: 7

摘要

描述了一种具有嵌入式闪存和基于sram的FPGA的1 GOPS动态可重构处理单元，用于图像/语音处理/识别应用。代码、数据和FPGA位流存储在嵌入式闪存中，可通过3个特定内容的64 b I/O端口独立访问，峰值读取速率为1.2 GB/s。该系统采用0.18 /spl mu/m的2P 6M CMOS闪存技术，芯片面积为70 mm/sup / 2/。

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A 1 GOPS reconfigurable signal processing IC with embedded FPGA and 3-port 1.2 GB/s flash memory subsystem

A 1 GOPS dynamically reconfigurable processing unit with embedded flash memory and SRAM-based FPGA for image/voice processing/recognition applications is described. Code, data and FPGA bitstreams are stored in the embedded flash memory and are independently accessible through 3 content-specific, 64 b I/O ports with a peak read rate of 1.2 GB/s. The system is implemented in a 0.18 /spl mu/m 2P 6M CMOS flash technology with a chip area of 70 mm/sup 2/.

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来源期刊

2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.

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