Strained SOI technology for high-performance, low-power CMOS applications

Abstract

Advantages of strained-SOI CMOS and the impact on circuit performance are presented from the viewpoint of ring oscillator speed, floating body effects, threshold voltage control and gate leakage reduction. Circuit performance enhancement of about 1.7 times over conventional SOI CMOS is verified experimentally at 0.95/spl mu/m gate lengths and theoretically expected even at gate lengths of 50nm.