Impact of dielectric relaxation on a 14 b pipeline ADC in 3 V SiGe BiCMOS

Abstract

Dielectric relaxation in PECVD SiN capacitors of a 45 GHz 0.4 /spl mu/m SiGe BiCMOS process degrades performance even at low frequencies. In the design of pipelined 14 b 70 MS/s ADC, the effects of dielectric relaxation are identified via behavioral/circuit simulations and ad-hoc tests. After LPCVD oxide capacitors are introduced, a 5.3/spl times/5.3 mm/sup 2/ test chip delivers 72 dB SNR, 81 dBc SFDR, and 11.5 ENOB at 70 MS/s with a 1 MHz input. The IC dissipates 1 W from 3.3 V.