2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.最新文献

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On-chip interconnect for mm-wave applications using an all-copper technology and wavelength reduction 片上互连毫米波应用使用全铜技术和波长减少
Tak Shun D. Cheung, John R. Long, K. Vaed, Richard Volant, A. Chinthakindi, C. Schnabel, J. Florkey, Kenneth Stein
{"title":"On-chip interconnect for mm-wave applications using an all-copper technology and wavelength reduction","authors":"Tak Shun D. Cheung, John R. Long, K. Vaed, Richard Volant, A. Chinthakindi, C. Schnabel, J. Florkey, Kenneth Stein","doi":"10.1109/ISSCC.2003.1234353","DOIUrl":"https://doi.org/10.1109/ISSCC.2003.1234353","url":null,"abstract":"Transmission lines are implemented using an all-copper backend developed for RF and microwave applications. Wavelength reduction is used to achieve a Q factor >20 from 20GHz to 40GHz, about three times higher than conventional transmission lines implemented with the same technology. It has 0.3dB/mm loss, and reduces the wavelength of a conventional transmission line by half thereby minimizing the space for on-chip microwave devices.","PeriodicalId":171288,"journal":{"name":"2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-02-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133916194","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 99
A 5 GHz floating point multiply-accumulator in 90 nm dual V/sub T/ CMOS 基于90nm双V/sub / CMOS的5 GHz浮点乘法累加器
S. Vangal, Y. Hoskote, D. Somasekhar, V. Erraguntla, J. Howard, G. Ruhl, V. Veeramachaneni, D. Finan, S. Mathew, N. Borkar
{"title":"A 5 GHz floating point multiply-accumulator in 90 nm dual V/sub T/ CMOS","authors":"S. Vangal, Y. Hoskote, D. Somasekhar, V. Erraguntla, J. Howard, G. Ruhl, V. Veeramachaneni, D. Finan, S. Mathew, N. Borkar","doi":"10.1109/ISSCC.2003.1234322","DOIUrl":"https://doi.org/10.1109/ISSCC.2003.1234322","url":null,"abstract":"A 32 b single-cycle floating point accumulator that uses base 32 and carry-save format with delayed addition is described. Combined algorithmic, logic and circuit techniques enable multiply-accumulate operation at 5 GHz. In a 90 nm 7M dual-V/sub T/ CMOS process, the 2 mm/sup 2/ prototype contains 230K transistors and dissipates 1.2 W at 5 GHz, 1.2 V and 25/spl deg/C.","PeriodicalId":171288,"journal":{"name":"2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-02-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134020955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
A 1.2 Gb/s/pin double data rate SDRAM with on-die-termination 一个1.2 Gb/s/引脚双数据速率SDRAM,具有模端端
Ho-Young Song, Seong-Jin Jang, J. Kwak, Cheol Su Kim, Chang Man Kang, D. Jeong, Y. Park, Min-Sang Park, Kyoung Su Byun, Woo-Jin Lee, Young-Cheol Cho, Won-Hwa Shin, Young-Uk Jang, Seokwon Hwang, Young-Hyun Jun, Sooin Cho
{"title":"A 1.2 Gb/s/pin double data rate SDRAM with on-die-termination","authors":"Ho-Young Song, Seong-Jin Jang, J. Kwak, Cheol Su Kim, Chang Man Kang, D. Jeong, Y. Park, Min-Sang Park, Kyoung Su Byun, Woo-Jin Lee, Young-Cheol Cho, Won-Hwa Shin, Young-Uk Jang, Seokwon Hwang, Young-Hyun Jun, Sooin Cho","doi":"10.1109/ISSCC.2003.1234314","DOIUrl":"https://doi.org/10.1109/ISSCC.2003.1234314","url":null,"abstract":"For operating frequencies exceeding 500 MHz, the timing margin of the I/O interface is critical and requires the data input-output timing accuracy to be within 200 ps. To meet the requirement, the designed SDRAM adopts a digitally self-calibrated on-die-termination with linearity error of /spl plusmn/1% and achieves over 1.2 Gbps/pin stable operation by using window matching and latency control. The chip is fabricated in a 0.13 /spl mu/m triple-well DRAM process.","PeriodicalId":171288,"journal":{"name":"2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-02-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133662230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
A high density conduction based micro-DNA-identification array fabricated in a CMOS compatible process 一种以CMOS相容制程制造的高密度导电微dna识别阵列
M. Xue, Jiong Li, Zuhong Lu, Chuguang Feng, Zhikuan Zhang, P. Ko, M. Chan
{"title":"A high density conduction based micro-DNA-identification array fabricated in a CMOS compatible process","authors":"M. Xue, Jiong Li, Zuhong Lu, Chuguang Feng, Zhikuan Zhang, P. Ko, M. Chan","doi":"10.1109/ISSCC.2003.1234265","DOIUrl":"https://doi.org/10.1109/ISSCC.2003.1234265","url":null,"abstract":"A high-density CMOS-compatible DNA array fabricated using a modified metalization process is demonstrated. The array produces a conductivity difference of nine orders of magnitude for matched and single-based mismatched DNA molecules, which can be easily detected by a simple sensing circuit.","PeriodicalId":171288,"journal":{"name":"2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-02-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132143661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A 1.0 V 256 Mb SDRAM with offset-compensated direct sensing and charge-recycled precharge schemes 带有偏移补偿直接传感和充电回收预充电方案的1.0 V 256mb SDRAM
J. Sim, K. Kwon, J. Choi, S. Lee, D.M. Kim, H. Hwang, K. Chun, Y. Seo, H. Hwang, D.I. Seo, C. Kim, S. Cho
{"title":"A 1.0 V 256 Mb SDRAM with offset-compensated direct sensing and charge-recycled precharge schemes","authors":"J. Sim, K. Kwon, J. Choi, S. Lee, D.M. Kim, H. Hwang, K. Chun, Y. Seo, H. Hwang, D.I. Seo, C. Kim, S. Cho","doi":"10.1109/ISSCC.2003.1234312","DOIUrl":"https://doi.org/10.1109/ISSCC.2003.1234312","url":null,"abstract":"A 1.0 V, 256 Mb SDRAM is designed in a 0.1 /spl mu/m CMOS technology. For low voltage applications, an offset compensated direct current sensing scheme improves refresh time as well as sensing performance. A charge-recycled precharge reuses the word-line discharge current to generate the boosted voltage required for equalization without charge pumping. At 1.0 V, the access time is 25 ns and the current is 15 mA.","PeriodicalId":171288,"journal":{"name":"2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-02-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130041423","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 43mW Bluetooth transceiver with -91dBm sensitivity 43mW蓝牙收发器,灵敏度-91dBm
C. Cojocaru, T. Pamir, F. Balteanu, A. Namdar, D. Payer, I. Gheorghe, T. Lipan, K. Sheikh, J. Pingot, H. Paananen, M. Littow, M. Cloutier, E. MacRobbie
{"title":"A 43mW Bluetooth transceiver with -91dBm sensitivity","authors":"C. Cojocaru, T. Pamir, F. Balteanu, A. Namdar, D. Payer, I. Gheorghe, T. Lipan, K. Sheikh, J. Pingot, H. Paananen, M. Littow, M. Cloutier, E. MacRobbie","doi":"10.1109/ISSCC.2003.1234220","DOIUrl":"https://doi.org/10.1109/ISSCC.2003.1234220","url":null,"abstract":"A Bluetooth transceiver has -91dBm sensitivity while drawing 24mA from a 1.8V supply. The receiver has a low-IF path with 30dB image and 9dB co-channel rejection, 80dB of AGC, digital equalization and complex PLL demodulation. The transmitter uses direct two-point modulation and draws 18mA at +6dBm output power. The DS PLL settles in 100/spl mu/s. LDO regulators power the analog and digital sections.","PeriodicalId":171288,"journal":{"name":"2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-02-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124980565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 47
A 20-input 20-output 12.5Gb/s SiGe cross-point switch with less than 2ps RMS jitter 20输入20输出12.5Gb/s SiGe交叉点开关,RMS抖动小于2ps
H. Veenstra, P. Barre, E. van der Heijden, D. van Goor, N. Lecacheur, B. Fahs, G. Gloaguen, S. Clamagirand, O. Burg
{"title":"A 20-input 20-output 12.5Gb/s SiGe cross-point switch with less than 2ps RMS jitter","authors":"H. Veenstra, P. Barre, E. van der Heijden, D. van Goor, N. Lecacheur, B. Fahs, G. Gloaguen, S. Clamagirand, O. Burg","doi":"10.1109/ISSCC.2003.1234254","DOIUrl":"https://doi.org/10.1109/ISSCC.2003.1234254","url":null,"abstract":"A cross-point switch IC in 0.25/spl mu/m SiGe technology for optical networking applications with 20 inputs and 20 outputs achieves an aggregate bandwidth of 250Gb/s. Jitter remains below 2ps RMS and is achieved using impedance matched on-chip signal transfer. The 36mm/sup 2/ IC dissipates 4W from a 2.5V supply.","PeriodicalId":171288,"journal":{"name":"2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-02-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130142565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Timekeeping techniques for predicting and optimizing memory behavior 预测和优化内存行为的计时技术
Zhigang Hu, S. Kaxiras, M. Martonosi
{"title":"Timekeeping techniques for predicting and optimizing memory behavior","authors":"Zhigang Hu, S. Kaxiras, M. Martonosi","doi":"10.1109/ISSCC.2003.1234251","DOIUrl":"https://doi.org/10.1109/ISSCC.2003.1234251","url":null,"abstract":"Computer architects have long exploited observed memory referencing characteristics to optimize memory performance. We introduce timekeeping metrics for improving program memory performance and power dissipation. Performance and power results for previously proposed timekeeping structures are briefly summarized and implementation options are presented. Simulation focusses on implementation issues.","PeriodicalId":171288,"journal":{"name":"2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.","volume":"202 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-02-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121112209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A 2.7 Gb/s CDMA-interconnect transceiver chip set with multi-level signal data recovery for re-configurable VLSI systems 一种2.7 Gb/s cdma互连收发器芯片组,具有多级信号数据恢复功能,适用于可重构的VLSI系统
Zhiwei Xu, Hyunchol Shin, Jongsun Kim, M. Chang, C. Chien
{"title":"A 2.7 Gb/s CDMA-interconnect transceiver chip set with multi-level signal data recovery for re-configurable VLSI systems","authors":"Zhiwei Xu, Hyunchol Shin, Jongsun Kim, M. Chang, C. Chien","doi":"10.1109/ISSCC.2003.1234217","DOIUrl":"https://doi.org/10.1109/ISSCC.2003.1234217","url":null,"abstract":"A 2.7 Gb/s interconnect transceiver chip-set based on Code Division Multiple Access (CDMA) is described and implemented in 0.18 /spl mu/m CMOS technology to achieve real-time system re-configurability and multiple I/O communication. The transceiver chip-set, with an Alexander-type multi-level data recovery circuit, can reconfigure multiple I/O signal routes within a symbol period of 0.8 ns. The chip-set dissipates 74 mW and occupies 0.3 mm/sup 2/ per I/O pair.","PeriodicalId":171288,"journal":{"name":"2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.","volume":"261 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-02-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123103316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
An on-chip high speed serial communication method based on independent ring oscillators 基于独立环形振荡器的片上高速串行通信方法
S. Kimura, T. Hayakawa, T. Horiyama, M. Nakanishi, K. Watanabe
{"title":"An on-chip high speed serial communication method based on independent ring oscillators","authors":"S. Kimura, T. Hayakawa, T. Horiyama, M. Nakanishi, K. Watanabe","doi":"10.1109/ISSCC.2003.1234350","DOIUrl":"https://doi.org/10.1109/ISSCC.2003.1234350","url":null,"abstract":"An on-chip module to module serial data transfer method uses parallel-to-serial conversion with a high frequency clock generated by internal ring oscillators. Both sender and receiver have their own rings which are synchronized by a one bit control line. A 7.84mm/sup 2/ prototype in 0.18/spl mu/m technology operates from a 1GHz clock.","PeriodicalId":171288,"journal":{"name":"2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-02-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115861119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
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