利用移位平均VCDL的低抖动精确多相锁滞环

2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. Pub Date : 2003-02-09 DOI:10.1109/ISSCC.2003.1234373

Hsiang-Hui Chang, C. Sun, Shen-Iuan Liu

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引用次数: 36

摘要

在0.35/spl mu/m CMOS中，DLL使用移位平均VCDL来减少延迟级之间不匹配引起的时序误差，而无需额外的硬件。DLL可以产生精确的多相输出，具有改进的占空比、减少的倾斜误差和降低的抖动。与传统DLL相比，该设计在150MHz时将峰间抖动提高了1.4倍。

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A low-jitter and precise multiphase delay-locked loop using shifted averaging VCDL

The DLL, in 0.35/spl mu/m CMOS, uses the shifted averaging VCDL to reduce the mismatch-induced timing error among the delay stages without extra hardware. The DLL can generate precise multiphase outputs with improved duty cycle, reduced skew errors, and lowered jitter. Compared with a conventional DLL, this design improves the peak-to-peak jitter by a factor of 1.4 at 150MHz.

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来源期刊

2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.

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