H. Sakakibara, M. Nakayama, M. Kusunoki, K. Kurita, H. Otori, M. Hasegawa, S. Iwahashi, K. Higeta, T. Hanashima, H. Hayashi, K. Kuchimachi, K. Uehara, T. Nishiyama, M. Kume, K. Miyamoto, E. Kamada
{"title":"一个750MHz 144Mb高速缓存DRAM LSI，具有高速可扩展设计和可编程的高速功能阵列BIST","authors":"H. Sakakibara, M. Nakayama, M. Kusunoki, K. Kurita, H. Otori, M. Hasegawa, S. Iwahashi, K. Higeta, T. Hanashima, H. Hayashi, K. Kuchimachi, K. Uehara, T. Nishiyama, M. Kume, K. Miyamoto, E. Kamada","doi":"10.1109/ISSCC.2003.1234385","DOIUrl":null,"url":null,"abstract":"A 750MHz 144Mb cache DRAM LSI incorporates speed-scalable embedded DRAM and SRAM macros, and is realized using a logic-merged DRAM process. The LSI has a built-in at-speed test engine with programmable test pattern and timing, merging logic and memory test. The die area is 285mm/sup 2/ in a 0.18/spl mu/m 6M logic-merged DRAM process.","PeriodicalId":171288,"journal":{"name":"2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.","volume":"67 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-02-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"A 750MHz 144Mb cache DRAM LSI with speed scalable design and programmable at-speed function-array BIST\",\"authors\":\"H. Sakakibara, M. Nakayama, M. Kusunoki, K. Kurita, H. Otori, M. Hasegawa, S. Iwahashi, K. Higeta, T. Hanashima, H. Hayashi, K. Kuchimachi, K. Uehara, T. Nishiyama, M. Kume, K. Miyamoto, E. Kamada\",\"doi\":\"10.1109/ISSCC.2003.1234385\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 750MHz 144Mb cache DRAM LSI incorporates speed-scalable embedded DRAM and SRAM macros, and is realized using a logic-merged DRAM process. The LSI has a built-in at-speed test engine with programmable test pattern and timing, merging logic and memory test. The die area is 285mm/sup 2/ in a 0.18/spl mu/m 6M logic-merged DRAM process.\",\"PeriodicalId\":171288,\"journal\":{\"name\":\"2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.\",\"volume\":\"67 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2003-02-09\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.2003.1234385\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2003.1234385","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 750MHz 144Mb cache DRAM LSI with speed scalable design and programmable at-speed function-array BIST
A 750MHz 144Mb cache DRAM LSI incorporates speed-scalable embedded DRAM and SRAM macros, and is realized using a logic-merged DRAM process. The LSI has a built-in at-speed test engine with programmable test pattern and timing, merging logic and memory test. The die area is 285mm/sup 2/ in a 0.18/spl mu/m 6M logic-merged DRAM process.
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