2012 IEEE International Interconnect Technology Conference最新文献

筛选
英文 中文
56 nm pitch copper dual-damascene interconnects with triple pitch split metal and double pitch split via 56纳米螺距铜双damascene互连与三螺距拆分金属和双螺距拆分通孔
2012 IEEE International Interconnect Technology Conference Pub Date : 2012-06-04 DOI: 10.1109/IITC.2012.6251637
J. Chen, C. Waskiewicz, S. Fan, S. Halle, C. Koay, Yongan Xu, N. Saulnier, Chiahsun Tseng, Y. Yin, Y. Mignot, M. Beard, B. Morris, D. Horak, S. Mignot, H. Shobha, M. Sankarapandian, O. van der Straten, J. Kelly, D. Canaperi, E. Mclellan, C. Boye, T. Levin, Juntao Li, J. Demarest, S. Choi, E. Huang, L. Liemann, B. Haran, J. Arnold, M. Colburn, L. Clevenger, T. Spooner
{"title":"56 nm pitch copper dual-damascene interconnects with triple pitch split metal and double pitch split via","authors":"J. Chen, C. Waskiewicz, S. Fan, S. Halle, C. Koay, Yongan Xu, N. Saulnier, Chiahsun Tseng, Y. Yin, Y. Mignot, M. Beard, B. Morris, D. Horak, S. Mignot, H. Shobha, M. Sankarapandian, O. van der Straten, J. Kelly, D. Canaperi, E. Mclellan, C. Boye, T. Levin, Juntao Li, J. Demarest, S. Choi, E. Huang, L. Liemann, B. Haran, J. Arnold, M. Colburn, L. Clevenger, T. Spooner","doi":"10.1109/IITC.2012.6251637","DOIUrl":"https://doi.org/10.1109/IITC.2012.6251637","url":null,"abstract":"This work demonstrates the building of a 56 nm pitch copper dual damascene interconnects which connects to the local interconnect level. This M1/V0 dual-damascene used a triple pitch split bi-directional M1 and a double pitch split contact (V0) scheme where the local interconnects are with double pitch split in each direction, respectively. This scheme will provide great design flexibility for the advanced logic circuits. The patterning scheme is multiple negative tone development lithography-etch. A memorization layer is utilized in the triple patterned M1 and the double patterned V0 levels, respectively. After transferring the two via levels into the metal memorization layer, a self-aligned-via (SAV) RIE scheme was used to create vias confined by line trenches such that via to line spacing is maximized for better reliability. Seven litho/etch steps (LIP1/LIP2/V0C1/V0C2/M1P1/M1P2/M1P3) were employed to present this revolutionary interconnects.","PeriodicalId":165741,"journal":{"name":"2012 IEEE International Interconnect Technology Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125599693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Low-k interconnect stack with metal-insulator-metal capacitors for 22nm high volume manufacturing 低k互连堆栈与金属绝缘体-金属电容器22nm大批量生产
2012 IEEE International Interconnect Technology Conference Pub Date : 2012-06-04 DOI: 10.1109/IITC.2012.6251663
D. Ingerly, A. Agrawal, R. Ascázubi, A. Blattner, M. Buehler, V. Chikarmane, B. Choudhury, F. Cinnor, C. Ege, C. Ganpule, T. Glassman, R. Grover, P. Hentges, J. Hicks, D. Jones, A. Kandas, H. Khan, N. Lazo, K. Lee, H. Liu, A. Madhavan, R. McFadden, T. Mule, D. Parsons, P. Parthangal, S. Rangaraj, D. Rao, J. Roesler, A. Schmitz, M. Sharma, J. Shin, Y. Shusterman, N. Speer, P. Tiwari, G. Wang, P. Yashar, K. Mistry
{"title":"Low-k interconnect stack with metal-insulator-metal capacitors for 22nm high volume manufacturing","authors":"D. Ingerly, A. Agrawal, R. Ascázubi, A. Blattner, M. Buehler, V. Chikarmane, B. Choudhury, F. Cinnor, C. Ege, C. Ganpule, T. Glassman, R. Grover, P. Hentges, J. Hicks, D. Jones, A. Kandas, H. Khan, N. Lazo, K. Lee, H. Liu, A. Madhavan, R. McFadden, T. Mule, D. Parsons, P. Parthangal, S. Rangaraj, D. Rao, J. Roesler, A. Schmitz, M. Sharma, J. Shin, Y. Shusterman, N. Speer, P. Tiwari, G. Wang, P. Yashar, K. Mistry","doi":"10.1109/IITC.2012.6251663","DOIUrl":"https://doi.org/10.1109/IITC.2012.6251663","url":null,"abstract":"We describe interconnect features for Intel's 22nm high-performance logic technology, with metal-insulator-metal capacitors and nine layers of interconnects. Metal-1 through Metal-6 feature a new ultra-low-k carbon doped oxide (CDO) and a low-k etch stop. Metal-7 and Metal-8 use a low-k CDO. New materials and process optimization provide 13-18% capacitance improvement. Single-exposure patterning for 80nm pitch layers makes the process cost-effective.","PeriodicalId":165741,"journal":{"name":"2012 IEEE International Interconnect Technology Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126697168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 46
A novel LWR reduction approach to enhance reliability performance in ultra-thin barrier/porous low-k (K<2.4) interconnect 一种新的LWR降低方法,提高超薄屏障/多孔低k (K&#60;2.4)互连的可靠性性能
2012 IEEE International Interconnect Technology Conference Pub Date : 2012-06-04 DOI: 10.1109/IITC.2012.6251569
C. W. Lu, T. Tsai, Y. Chang, C. Tsai, S. Singh, T. Huang, H. Yao, C. J. Lee, T. Bao, S. Shue, C. H. Yu
{"title":"A novel LWR reduction approach to enhance reliability performance in ultra-thin barrier/porous low-k (K&#60;2.4) interconnect","authors":"C. W. Lu, T. Tsai, Y. Chang, C. Tsai, S. Singh, T. Huang, H. Yao, C. J. Lee, T. Bao, S. Shue, C. H. Yu","doi":"10.1109/IITC.2012.6251569","DOIUrl":"https://doi.org/10.1109/IITC.2012.6251569","url":null,"abstract":"This study evaluated plasma treatment processes on 193i and EUV photoresist to improve the line width roughness (LWR) performance in porous low-k/ultra-thin barrier Cu interconnect. We successfully demonstrated 20% LWR reduction for 193i PR and 11% for EUV PR. Furthermore, the influence of LWR on reliability was evaluated on 45nm line-width test vehicle. A boost of 10 times Time Dependent Dielectric Breakdown (TDDB) and 2 times Eelectrical Migration (EM) was demonstrated.","PeriodicalId":165741,"journal":{"name":"2012 IEEE International Interconnect Technology Conference","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129650924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
What lies ahead for interconnects and devices 互连和设备的未来是什么
2012 IEEE International Interconnect Technology Conference Pub Date : 2012-06-04 DOI: 10.1109/IITC.2012.6251563
M. Mayberry
{"title":"What lies ahead for interconnects and devices","authors":"M. Mayberry","doi":"10.1109/IITC.2012.6251563","DOIUrl":"https://doi.org/10.1109/IITC.2012.6251563","url":null,"abstract":"Predicting what lies ahead is fraught with peril as our ability to see is dependent on where and how we look. We are in a regime where nanometer advances can still deliver major performance increases. Our immediate directions are clear but many choices will need to be made in the next few years to be ready for technology in 2020 and beyond.","PeriodicalId":165741,"journal":{"name":"2012 IEEE International Interconnect Technology Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127903023","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Novel miniaturized packaging for implantable electronic devices 可植入电子设备的新型小型化封装
2012 IEEE International Interconnect Technology Conference Pub Date : 2012-06-04 DOI: 10.1109/IITC.2012.6251669
K. Qian, M. O. de Beeck, G. Bryce, K. Malachowski, C. van Hoof
{"title":"Novel miniaturized packaging for implantable electronic devices","authors":"K. Qian, M. O. de Beeck, G. Bryce, K. Malachowski, C. van Hoof","doi":"10.1109/IITC.2012.6251669","DOIUrl":"https://doi.org/10.1109/IITC.2012.6251669","url":null,"abstract":"A novel biocompatible packaging process for implantable electronic systems is described, combining excellent biocompatibility and hermeticity with extreme miniaturization. Biocompatible and clean room compatible materials and integration processes are evaluated and selected for die encapsulation and interconnection. Cytotoxicity, diffusion tests and corrosion tests using DI water and more aggressive bio-fluids demonstrated promising performance of the packaging.","PeriodicalId":165741,"journal":{"name":"2012 IEEE International Interconnect Technology Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128291694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Electrical performances and quality investigations of integrated bonded structures and TSVs for 3D interconnects 三维互连用集成键合结构和tsv的电性能和质量研究
2012 IEEE International Interconnect Technology Conference Pub Date : 2012-06-04 DOI: 10.1109/IITC.2012.6251636
K. N. Chen, Y. J. Chang, C. Ko, S. Hsu, H. Y. Chen, C. Hsiao, T. Yu, Y. -. Chen, W. Lo
{"title":"Electrical performances and quality investigations of integrated bonded structures and TSVs for 3D interconnects","authors":"K. N. Chen, Y. J. Chang, C. Ko, S. Hsu, H. Y. Chen, C. Hsiao, T. Yu, Y. -. Chen, W. Lo","doi":"10.1109/IITC.2012.6251636","DOIUrl":"https://doi.org/10.1109/IITC.2012.6251636","url":null,"abstract":"The integration of TSVs and bonded structures is an important topic in 3D integration. In this study, fine Cu TSVs and various bonded structures, including Cu/Sn micro-bumps, Cu bond pads, and Cu alloy structures, are integrated and demonstrated. Electrical performances, morphology investigations, and reliability investigations of TSVs, bonded bumps/pads, and the integrated structures are studied. For a wellfabricated 3D interconnect structure, excellent electrical performance and mechanical strength with stable reliability behavior can be achieved.","PeriodicalId":165741,"journal":{"name":"2012 IEEE International Interconnect Technology Conference","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133816767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Inline Low-k damage detection of Cu/Low-k interconnect using micro beam IR method 微束红外法在线检测Cu/Low-k互连的低k损伤
2012 IEEE International Interconnect Technology Conference Pub Date : 2012-06-04 DOI: 10.1109/IITC.2012.6251642
K. Goto, Y. Oka, N. Miura, M. Matsuura, K. Asai
{"title":"Inline Low-k damage detection of Cu/Low-k interconnect using micro beam IR method","authors":"K. Goto, Y. Oka, N. Miura, M. Matsuura, K. Asai","doi":"10.1109/IITC.2012.6251642","DOIUrl":"https://doi.org/10.1109/IITC.2012.6251642","url":null,"abstract":"It has become more serious concern to quantify Low-k damage in Cu/Low-k interconnects. We investigated the relationship between the amount of OH group in Low-k material obtained from micro-beam IR method and the interconnect capacitance. And it was found that there is good correlation among them. Additionally, the micro-beam IR method sensitively detected modifications of amount of OH group for several kinds of treatment processes except for the NH3 plasma treatment prior to Cu diffusion barrier dielectric deposition.","PeriodicalId":165741,"journal":{"name":"2012 IEEE International Interconnect Technology Conference","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133463042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Novel Cu reflow seed process for Cu/low-k 64nm pitch dual damascene interconnects and beyond 铜/低钾64nm双硅互连的新型铜回流制粒工艺
2012 IEEE International Interconnect Technology Conference Pub Date : 2012-06-04 DOI: 10.1109/IITC.2012.6251656
K. Motoyama, O. van der Straten, H. Tomizawa, J. Maniscalco, S. T. Chen
{"title":"Novel Cu reflow seed process for Cu/low-k 64nm pitch dual damascene interconnects and beyond","authors":"K. Motoyama, O. van der Straten, H. Tomizawa, J. Maniscalco, S. T. Chen","doi":"10.1109/IITC.2012.6251656","DOIUrl":"https://doi.org/10.1109/IITC.2012.6251656","url":null,"abstract":"A novel Cu reflow seed process which utilizes PVD technology components has been demonstrated for 64nm pitch dual damascene interconnects. Prior to Cu electroplating, small features can be partially filled with Cu by this newly developed Cu reflow seed process. More than 60% improvement of via-chain yield is obtained by Cu reflow seed compared to conventional seed. A sacrificial Cu underlayer was applied to reduce barrier damage effects during Cu reflow seed processing, successfully suppressing any line resistance increase. This Cu reflow seed process is a promising candidate for improving Cu fill properties of 64nm pitch interconnects and beyond.","PeriodicalId":165741,"journal":{"name":"2012 IEEE International Interconnect Technology Conference","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130909070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Photoemission study of the growth of Mn silicate barrier layers on ultra low-k carbon doped oxide surfaces 锰硅酸盐阻挡层在超低k掺杂碳氧化物表面生长的光发射研究
2012 IEEE International Interconnect Technology Conference Pub Date : 2012-06-04 DOI: 10.1109/IITC.2012.6251643
J. Bogan, P. Casey, A. McCoy, G. Hughes
{"title":"Photoemission study of the growth of Mn silicate barrier layers on ultra low-k carbon doped oxide surfaces","authors":"J. Bogan, P. Casey, A. McCoy, G. Hughes","doi":"10.1109/IITC.2012.6251643","DOIUrl":"https://doi.org/10.1109/IITC.2012.6251643","url":null,"abstract":"In this study Mn silicate (MnSiO3) barrier layers were formed on ultra low dielectric constant (ULK) carbon doped oxide (CDO) surfaces, using both metallic Mn and oxidized Mn films. Using x-ray photoelectron spectroscopy (XPS) it has been shown that deposition of metallic Mn and partially oxidised Mn (MnOx where x <; 1) films on CDO surfaces results in the formation of both MnSiO3 and a Mn carbide species within the barrier layer region. Analysis suggests that Mn carbide species are formed through the depletion of C from the CDO structure, which may increase the dielectric constant of the CDO. It is also shown that the interaction of a fully oxidised Mn (MnOy where y ≥ 1) layer on CDO results in the growth of a MnSiO3 barrier layer free from Mn carbide, metallic Mn and Mn oxide. These studies indicate that Mn carbide is only formed on CDO surface in the presence of metallic Mn. Finally, the growth of MnSiO3 layers on CDO is shown to be self-limited by the availability of additional oxygen, beyond that found within the CDO layer.","PeriodicalId":165741,"journal":{"name":"2012 IEEE International Interconnect Technology Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125117216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Improved statistical analysis at low failure rates in Cu electromigration using an innovative multilink test structure 采用创新的多链路测试结构,改进了铜电迁移中低故障率的统计分析
2012 IEEE International Interconnect Technology Conference Pub Date : 2012-06-04 DOI: 10.1109/IITC.2012.6251668
F. Bana, D. Ney, L. Arnaud, Y. Wouters
{"title":"Improved statistical analysis at low failure rates in Cu electromigration using an innovative multilink test structure","authors":"F. Bana, D. Ney, L. Arnaud, Y. Wouters","doi":"10.1109/IITC.2012.6251668","DOIUrl":"https://doi.org/10.1109/IITC.2012.6251668","url":null,"abstract":"An innovative electromigration test structure is described in this paper. This new structure consisting of serial connected links is designed to address very early percentiles of lognormal electromigration failure time distribution and highlight extrinsic failures. The simplicity of implementation, data treatment and the correlation with elemental dual damascene test lines make this structure a pretty good candidate for the future of interconnects reliability.","PeriodicalId":165741,"journal":{"name":"2012 IEEE International Interconnect Technology Conference","volume":"12 S1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113971999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信