2012 IEEE International Interconnect Technology Conference最新文献

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Effects of CVD-W process on electrical properties in sub 2× nm flash devices CVD-W工艺对亚2xnm闪存器件电性能的影响
2012 IEEE International Interconnect Technology Conference Pub Date : 2012-06-04 DOI: 10.1109/IITC.2012.6251577
Hauk Han, Chan-Ho Lee, Hyunseok Lim, M. Lee
{"title":"Effects of CVD-W process on electrical properties in sub 2× nm flash devices","authors":"Hauk Han, Chan-Ho Lee, Hyunseok Lim, M. Lee","doi":"10.1109/IITC.2012.6251577","DOIUrl":"https://doi.org/10.1109/IITC.2012.6251577","url":null,"abstract":"The physical and electrical properties of chemical vapor deposition (CVD) tungsten (W) are evaluated in terms of W nucleation layer (SiH<sub>4</sub> and B<sub>2</sub>H<sub>6</sub> reduction). Moreover effects of W nucleation layer on contact resistance (Rc) for sub 2× nm device are also studied. The results show that electrical properties of W thin films are varied with nucleation layers. Our results reveal that W reductions gases determine the grain sizes of W films which influence both electrical and surface properties of W films. It also has been investigated that effect of boron (B) atoms in B<sub>2</sub>H<sub>6</sub> reduction W layer on P<sup>+</sup> Rc. Out-diffused B atoms from P<sup>+</sup> junction into silicide layer during post thermal process are compensated by B of B<sub>2</sub>H<sub>6</sub> reduction W layer, which result in no degradation of P<sup>+</sup> Rc despite of dopants loss at the contact interfaces. We reveal that tungsten nucleation layers are correlated with physical and electrical properties of W films and device performance.","PeriodicalId":165741,"journal":{"name":"2012 IEEE International Interconnect Technology Conference","volume":"129 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115214557","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Electrical and structural characterization of 150 nm CNT contacts with Cu damascene top metallization 150纳米碳纳米管接触铜damascene顶部金属化的电学和结构表征
2012 IEEE International Interconnect Technology Conference Pub Date : 2012-06-04 DOI: 10.1109/IITC.2012.6251670
M. V. Veen, Bart Vereecke, Masahito Sugiura, Y. Kashiwagi, X. Ke, D. Cott, J. Vanpaemel, P. Vereecken, S. Gendt, C. Huyghebaert, Zsolt Tokei
{"title":"Electrical and structural characterization of 150 nm CNT contacts with Cu damascene top metallization","authors":"M. V. Veen, Bart Vereecke, Masahito Sugiura, Y. Kashiwagi, X. Ke, D. Cott, J. Vanpaemel, P. Vereecken, S. Gendt, C. Huyghebaert, Zsolt Tokei","doi":"10.1109/IITC.2012.6251670","DOIUrl":"https://doi.org/10.1109/IITC.2012.6251670","url":null,"abstract":"This paper discusses the electrical and structural characterization of 150 nm diameter contacts filled with carbon nanotubes (CNTs) and a Cu damascene top metal. We present the first images of CNTs in direct contact with the top metal. A CNT tip clean before metallization reduced the single CNT contact hole resistance from 4.8 kΩ down to 2.8 kΩ (aspect ratio 2.4). The first basic electrical breakdown experiments with Kelvins resulted in high breakdown currents of 5-13 MA/cm2.","PeriodicalId":165741,"journal":{"name":"2012 IEEE International Interconnect Technology Conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128371428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
56nm-pitch low-k/Cu dual-damascene interconnects integration with sidewall image transfer (SIT) patterning scheme 56nm节距低k/Cu双砷互连集成与侧壁图像传输(SIT)模式方案
2012 IEEE International Interconnect Technology Conference Pub Date : 2012-06-04 DOI: 10.1109/IITC.2012.6251664
M. Tagami, K. Shimada, Y. Yin, M. Ishikawa, C. Waskiewicz, S.T. Chen, H. Shobha, E. Soda, N. Saulnier, J. Arnold, M. Colburn, T. Usui, T. Spooner
{"title":"56nm-pitch low-k/Cu dual-damascene interconnects integration with sidewall image transfer (SIT) patterning scheme","authors":"M. Tagami, K. Shimada, Y. Yin, M. Ishikawa, C. Waskiewicz, S.T. Chen, H. Shobha, E. Soda, N. Saulnier, J. Arnold, M. Colburn, T. Usui, T. Spooner","doi":"10.1109/IITC.2012.6251664","DOIUrl":"https://doi.org/10.1109/IITC.2012.6251664","url":null,"abstract":"Three metal level 56nm-pitch Cu dual damascene interconnects in k2.7 low-k ILD have been demonstrated by using sidewall-image-transfer (SIT) patterning scheme to investigate the feasibility of the SIT process for sub 50nm-pitch technology node. 45nm-pitch line resistance (R) and capacitance (C) simulation are performed to estimate the R-C variation for double patterning schemes. The photoresist mandrel SIT process for 56nm-pitch Cu line is investigated to develop the constant line pitch and less line edge roughness (LER). The basic electrical properties such as line open/short and via chain open/short yields are ~100%. The 56nm-pitch R-C variation is comparable to simulated 80nm-pitch R-C variation. The SIT patterning process is a strong candidate to improve the R-C variation for sub50nm-pitch technology nodes.","PeriodicalId":165741,"journal":{"name":"2012 IEEE International Interconnect Technology Conference","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116818814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Growth characteristics of Mn silicate barrier layers on SiO2 二氧化硅上锰硅酸盐阻挡层的生长特性
2012 IEEE International Interconnect Technology Conference Pub Date : 2012-06-04 DOI: 10.1109/IITC.2012.6251652
P. Casey, J. Bogan, A. McCoy, J. Lozano, P. Nellist, G. Hughes
{"title":"Growth characteristics of Mn silicate barrier layers on SiO2","authors":"P. Casey, J. Bogan, A. McCoy, J. Lozano, P. Nellist, G. Hughes","doi":"10.1109/IITC.2012.6251652","DOIUrl":"https://doi.org/10.1109/IITC.2012.6251652","url":null,"abstract":"Synchrotron radiation photoelectron spectroscopy (SRPES) is used to investigate the in-situ formation of ultra thin Mn silicate copper diffusion barrier layers on SiO2. It was shown that high temperature annealing results in the growth of Mn silicate, the stoichiometry of which was calculated to be MnSiO3. SRPES results also show that the interaction of metallic Mn with SiO2 is self limiting at high temperature. In a separate experiment the role of oxygen in determining the extent of the interaction between the deposited Mn and the SiO2 substrate was investigated. Using X-ray photoelectron spectroscopy (XPS) it has been shown that a metallic Mn film (~1 nm) cannot be fully converted to Mn silicate following vacuum annealing to 500°C. Transmission electron microscopy (TEM) analysis suggests the maximum MnSiO3 layer thickness obtainable using metallic Mn is ~1.7 nm. In contrast, a ~1 nm partially oxidized Mn film can be fully converted to Mn silicate following thermal annealing to 400°C, forming a MnSiO3 layer with a measured thickness of 2.6 nm. TEM analysis also clearly shows that MnSiO3 growth results in a corresponding reduction in SiO2 layer thickness. Based on these results it is suggested that the presence of Mn oxide species at the Mn/SiO2 interface facilitates the conversion of SiO2 to MnSiO3.","PeriodicalId":165741,"journal":{"name":"2012 IEEE International Interconnect Technology Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116662620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Effect of W doping on bipolar resistive switching behavior of TiN/W:NbOx/Pt device W掺杂对TiN/W:NbOx/Pt器件双极电阻开关行为的影响
2012 IEEE International Interconnect Technology Conference Pub Date : 2012-06-04 DOI: 10.1109/IITC.2012.6251647
Kyumin Lee, Jonggi Kim, Sunghoon Lee, Sunghoon Park, H. Sohn
{"title":"Effect of W doping on bipolar resistive switching behavior of TiN/W:NbOx/Pt device","authors":"Kyumin Lee, Jonggi Kim, Sunghoon Lee, Sunghoon Park, H. Sohn","doi":"10.1109/IITC.2012.6251647","DOIUrl":"https://doi.org/10.1109/IITC.2012.6251647","url":null,"abstract":"In our study, resistive switching characteristics of TiN/ W:NbOx/Pt with tungsten doping concentration are investigated. We demonstrated that an increase of oxygen vacancies with increasing the concentration of W doping in W:NbOx films. The W:NbOx specimens show bipolar resistive switching and switching current could be controlled by tungsten doping concentration in NbOx. It is concluded that oxygen vacancies concentration plays an important role in bipolar resistive switching characteristic of W:NbOx.","PeriodicalId":165741,"journal":{"name":"2012 IEEE International Interconnect Technology Conference","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122156321","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Electrical characterization of carbon nanotube vertical interconnects with different lengths and widths 不同长度和宽度的碳纳米管垂直互连的电学特性
2012 IEEE International Interconnect Technology Conference Pub Date : 2012-06-04 DOI: 10.1109/IITC.2012.6251578
S. Vollebregt, R. Ishihara, F. Tichelaar, J. van der Cingel, K. Beenakker
{"title":"Electrical characterization of carbon nanotube vertical interconnects with different lengths and widths","authors":"S. Vollebregt, R. Ishihara, F. Tichelaar, J. van der Cingel, K. Beenakker","doi":"10.1109/IITC.2012.6251578","DOIUrl":"https://doi.org/10.1109/IITC.2012.6251578","url":null,"abstract":"Carbon nanotubes (CNT) can be an attractive candidate for vertical interconnects due to their bottom-up nature and excellent electrical and thermal properties. In this paper we demonstrate low temperature high-density CNT growth and results of electrical characterization. We determined that our CNT contact resistance is low compared to other results in literature, likely caused by a good top contact. The CNT display good uniformity over the wafer and the calculated resistivity of 10 mΩ-cm is among the lowest in literature.","PeriodicalId":165741,"journal":{"name":"2012 IEEE International Interconnect Technology Conference","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126539263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
How to address metallization and reliability challenges in today and tomorrows technology nodes? 如何应对当今和未来技术节点的金属化和可靠性挑战?
2012 IEEE International Interconnect Technology Conference Pub Date : 2012-06-04 DOI: 10.1109/IITC.2012.6251655
A. Preusse, J. Hahn, T. Chowdhury, B. Hintze, R. Liske, M. Nopper, U. Stoeckgen
{"title":"How to address metallization and reliability challenges in today and tomorrows technology nodes?","authors":"A. Preusse, J. Hahn, T. Chowdhury, B. Hintze, R. Liske, M. Nopper, U. Stoeckgen","doi":"10.1109/IITC.2012.6251655","DOIUrl":"https://doi.org/10.1109/IITC.2012.6251655","url":null,"abstract":"While dual damascene integration for current technologies is often cited for its challenges in regard to patterning and demands on lithography hardand software. Metallization for features with aspect ratios in the range of 4:1 as well as line widths with 40nm and shrinking is thought to be manageable with established technologies. Void free fill of lines and vias is mandatory yet reliability and line resistance gaining importance from one technology node to the next. Methods to enhance reliability are abound however which of the solutions are extendible to future technology nodes depends on a variety of parameters. The before mentioned topics on metallization challenges as well as choices to enhance reliability will be discussed in the paper.","PeriodicalId":165741,"journal":{"name":"2012 IEEE International Interconnect Technology Conference","volume":"1098 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116044655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Fine pitch TSV integration in silicon micropin-fin heat sinks for 3D ICs 用于3D集成电路的硅微针翅片散热器中的细间距TSV集成
2012 IEEE International Interconnect Technology Conference Pub Date : 2012-06-04 DOI: 10.1109/IITC.2012.6251587
A. Dembla, Yue Zhang, Muhannad S. Bakir
{"title":"Fine pitch TSV integration in silicon micropin-fin heat sinks for 3D ICs","authors":"A. Dembla, Yue Zhang, Muhannad S. Bakir","doi":"10.1109/IITC.2012.6251587","DOIUrl":"https://doi.org/10.1109/IITC.2012.6251587","url":null,"abstract":"Future high performance 3D systems require a systematic co-design of their electrical interconnect network and their heat removal mechanism. This paper presents fine pitch (20μm) and high aspect ratio (18:1) TSVs integrated in a micropin-fin heat sink capable of removing power density of 100W/cm2 and resulting in junction temperatures below 50°C.","PeriodicalId":165741,"journal":{"name":"2012 IEEE International Interconnect Technology Conference","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133809211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Optical interconnect technology for 3D LSI and neural engineering applications 用于三维大规模集成电路和神经工程应用的光互连技术
2012 IEEE International Interconnect Technology Conference Pub Date : 2012-06-04 DOI: 10.1109/IITC.2012.6251672
T. Tanaka, A. Noriki, T. Fukushima, K. Lee, M. Koyanagi
{"title":"Optical interconnect technology for 3D LSI and neural engineering applications","authors":"T. Tanaka, A. Noriki, T. Fukushima, K. Lee, M. Koyanagi","doi":"10.1109/IITC.2012.6251672","DOIUrl":"https://doi.org/10.1109/IITC.2012.6251672","url":null,"abstract":"To realize very high performance computing system, we have proposed a novel opto-electronic 3-D LSI in which both electrical and optical devices are integrated. For seamless optical interconnects both vertically and horizontally, through Si photonic via (TSPV) and unidirectional optical coupler (UDOC) are indispensable. We succeeded in fabrication of conventional TSVs and the TSPVs comprising Si core and SiO2 cladding simultaneously. We also developed optical interconnects embedded in the intelligent Si neural probe. Both neuronal signal recording and cell optical stimulation can be achieved with the Si neural probe having optical interconnects. Our neural probe becomes a novel tool for brain function analysis, neurophysiology, and optgenetics.","PeriodicalId":165741,"journal":{"name":"2012 IEEE International Interconnect Technology Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128058526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Direct copper electrodeposition on a chemical vapor-deposited ruthenium seed layer for through-silicon vias 在化学气相沉积钌种子层上直接电沉积铜,用于硅通孔
2012 IEEE International Interconnect Technology Conference Pub Date : 2012-06-04 DOI: 10.1109/IITC.2012.6251644
P. Shi, J. Enloe, R. Van Den Boom, B. Sapp
{"title":"Direct copper electrodeposition on a chemical vapor-deposited ruthenium seed layer for through-silicon vias","authors":"P. Shi, J. Enloe, R. Van Den Boom, B. Sapp","doi":"10.1109/IITC.2012.6251644","DOIUrl":"https://doi.org/10.1109/IITC.2012.6251644","url":null,"abstract":"Direct plating of Cu on Ru for dual damascene and high aspect ratio through-silicon via (TSV) structures requires high nucleation density and rapid coalescence of the Cu nuclei, which may be achieved by incorporating strong suppressors in the plating solution. Atotech Spherolyte plating chemistry, containing a unique strong suppressor, is able to generate a nucleation density greater than 1012 cm-2. No pretreatment of the Ru surface is necessary. Void-free, bottom-up fill has been repeatedly demonstrated within 40 min using this chemistry for 5 μm × 50 μm TSV structures without Cu seeds. Material characterizations including time-of-flight secondary ion mass spectrometry (ToF-SIMS) and electron backscatter diffraction (EBSD) analyses of the plated TSVs have been conducted and discussed.","PeriodicalId":165741,"journal":{"name":"2012 IEEE International Interconnect Technology Conference","volume":"305 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114526991","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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