A. Preusse, J. Hahn, T. Chowdhury, B. Hintze, R. Liske, M. Nopper, U. Stoeckgen
{"title":"How to address metallization and reliability challenges in today and tomorrows technology nodes?","authors":"A. Preusse, J. Hahn, T. Chowdhury, B. Hintze, R. Liske, M. Nopper, U. Stoeckgen","doi":"10.1109/IITC.2012.6251655","DOIUrl":null,"url":null,"abstract":"While dual damascene integration for current technologies is often cited for its challenges in regard to patterning and demands on lithography hardand software. Metallization for features with aspect ratios in the range of 4:1 as well as line widths with 40nm and shrinking is thought to be manageable with established technologies. Void free fill of lines and vias is mandatory yet reliability and line resistance gaining importance from one technology node to the next. Methods to enhance reliability are abound however which of the solutions are extendible to future technology nodes depends on a variety of parameters. The before mentioned topics on metallization challenges as well as choices to enhance reliability will be discussed in the paper.","PeriodicalId":165741,"journal":{"name":"2012 IEEE International Interconnect Technology Conference","volume":"1098 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 IEEE International Interconnect Technology Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IITC.2012.6251655","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
While dual damascene integration for current technologies is often cited for its challenges in regard to patterning and demands on lithography hardand software. Metallization for features with aspect ratios in the range of 4:1 as well as line widths with 40nm and shrinking is thought to be manageable with established technologies. Void free fill of lines and vias is mandatory yet reliability and line resistance gaining importance from one technology node to the next. Methods to enhance reliability are abound however which of the solutions are extendible to future technology nodes depends on a variety of parameters. The before mentioned topics on metallization challenges as well as choices to enhance reliability will be discussed in the paper.