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2012 IEEE International Interconnect Technology Conference最新文献

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Improving TDDB reliability in Cu damascene by modulating ESL structure 通过调制ESL结构提高铜damascene中TDDB的可靠性
2012 IEEE International Interconnect Technology Conference Pub Date : 2012-06-04 DOI: 10.1109/IITC.2012.6251573
C. T. Chang, H. L. Chang
{"title":"Improving TDDB reliability in Cu damascene by modulating ESL structure","authors":"C. T. Chang, H. L. Chang","doi":"10.1109/IITC.2012.6251573","DOIUrl":"https://doi.org/10.1109/IITC.2012.6251573","url":null,"abstract":"Low k time-dependent dielectric breakdown (TDDB) is increasing becoming a major issue at 28 nm and beyond. Although TDDB models, such as E model, the √E model and the 1/E model, have been extensively explored, determining the BEOL processing direction for TDDB warrants further study. This study attempts to determine whether the thickness of the etching stop layer film influences the electron conduction mechanism. Cu damascene structures were designed following three approaches with ESL in various thicknesses. They were Co/ESL=0A-550A (LK: SiCO k= 3.1), Cu/ESL=0A-275A (ELK: SiCO k=2.5) and Co/ESL=0A-275A (ELK: SiCO k=2.5). Analytical results demonstrated superior breakdown fields of 8.5 MV/cm, 7.5 MV/cm and 7.5 MV/cm for Co/ESL=0A (SiCO k=3.1), Cu/ESL = 0A (SiCO k=2.5) and Co/ESL = 0A (SiCO k=2.5), respectively. TDDB results further reveal that the ESL=0A structure is essential to a long TDDB lifetime, because electrons are conducted through the ESL bulk film. The mechanism of TDDB improvement is considered to be the absence of ESL, the modified metal/LK electrical potential and the negligibility of interfacial LK/LK surface defects.","PeriodicalId":165741,"journal":{"name":"2012 IEEE International Interconnect Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121154062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Comparison of mechanical stresses of Cu Through-Silicon Via (TSV) samples fabricated by Hynix vs. SEMATECH using synchrotron X-ray microdiffraction for 3-D integration and reliability Hynix和SEMATECH制造的Cu Through-Silicon Via (TSV)样品的机械应力比较，采用同步加速器x射线微衍射进行三维集成和可靠性比较
2012 IEEE International Interconnect Technology Conference Pub Date : 2012-06-04 DOI: 10.1109/IITC.2012.6251661
A. Budiman, H. Shin, B. Kim, S. Hwang, H.-Y Son, M. Suh, Q. Chung, Kwang-yoo Byun, Young‐Chang Joo, R. Caramto, L. Smith, M. Kunz, N. Tamura
{"title":"Comparison of mechanical stresses of Cu Through-Silicon Via (TSV) samples fabricated by Hynix vs. SEMATECH using synchrotron X-ray microdiffraction for 3-D integration and reliability","authors":"A. Budiman, H. Shin, B. Kim, S. Hwang, H.-Y Son, M. Suh, Q. Chung, Kwang-yoo Byun, Young‐Chang Joo, R. Caramto, L. Smith, M. Kunz, N. Tamura","doi":"10.1109/IITC.2012.6251661","DOIUrl":"https://doi.org/10.1109/IITC.2012.6251661","url":null,"abstract":"One key to enable the successful implementation of 3-D interconnects using Through-Silicon Via (TSV) is the control of the mechanical stresses. The synchrotron-sourced X-ray microdiffraction technique has been recognized to allow some important advantages compared to other techniques. Using this approach, we have studied Cu TSV samples from Hynix, Inc. as well as from SEMATECH and found interesting differences in the stress states of the Cu TSV. We proposed an explanation of the observed differences. This understanding could lead to improved stress control in Cu TSV as well as to reduce the impact to the silicon electron mobility.","PeriodicalId":165741,"journal":{"name":"2012 IEEE International Interconnect Technology Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130113326","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Microprobing the mechanical effects of varying dielectric porosity in advanced interconnect structures 微探测先进互连结构中介电孔隙率变化的力学效应
2012 IEEE International Interconnect Technology Conference Pub Date : 2012-06-04 DOI: 10.1109/IITC.2012.6251666
A. Hsing, H. Geisler, V. Ryan, M. Cheng, K. Machani, D. Breuer, M. Lehr, J. Paul, F. Iacopi, R. Dauskardt
{"title":"Microprobing the mechanical effects of varying dielectric porosity in advanced interconnect structures","authors":"A. Hsing, H. Geisler, V. Ryan, M. Cheng, K. Machani, D. Breuer, M. Lehr, J. Paul, F. Iacopi, R. Dauskardt","doi":"10.1109/IITC.2012.6251666","DOIUrl":"https://doi.org/10.1109/IITC.2012.6251666","url":null,"abstract":"Chip-package interaction has become a major concern due to increasingly porous low-K dielectrics. During the packaging process, shear stresses are exerted on fragile interconnect structures. We use a microprobe metrology system to experimentally measure how interconnect stacks with different dielectric porosities behave under various shear loading conditions and a wide range of temperatures.","PeriodicalId":165741,"journal":{"name":"2012 IEEE International Interconnect Technology Conference","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114612474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Comparative study on ALD/CVD-Co(W) films as a single barrier/liner layer for 22−1x nm generation interconnects ALD/CVD-Co(W)薄膜作为22−1x nm一代互连的单势垒/衬垫层的比较研究
2012 IEEE International Interconnect Technology Conference Pub Date : 2012-06-04 DOI: 10.1109/IITC.2012.6251657
H. Shimizu, H. Wojcik, K. Shima, Y. Kobayashi, T. Momose, J. Bartha, Y. Shimogaki
{"title":"Comparative study on ALD/CVD-Co(W) films as a single barrier/liner layer for 22−1x nm generation interconnects","authors":"H. Shimizu, H. Wojcik, K. Shima, Y. Kobayashi, T. Momose, J. Bartha, Y. Shimogaki","doi":"10.1109/IITC.2012.6251657","DOIUrl":"https://doi.org/10.1109/IITC.2012.6251657","url":null,"abstract":"ALD-Co(W) was found to have a potential to replace the conventional PVD-Ta/TaN bi-layer in further shrinking interconnects as a single-layered barrier/liner material. We could confirm good barrier property of CVD/ALD-Co(W) film by BTS-TVS method after 350°C annealing. ALD-Co(W) showed lower resistivity of 60 μΩ-cm and good adhesion to Cu. Complete trench filling with Co(W) followed by Cu seed deposition was demonstrated. These properties were confirmed to be derived from W stuffing into grain boundaries of oxygen-free ALD-Co(W) films. We would like to suggest ALD-Co(W) as a next-generation barrier/liner layer for future development.","PeriodicalId":165741,"journal":{"name":"2012 IEEE International Interconnect Technology Conference","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114845378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Integration of a k=2.3 spin-on polymer for the sub-28nm technology node using EUV lithography 利用EUV光刻技术集成k=2.3自旋聚合物的亚28nm技术节点
2012 IEEE International Interconnect Technology Conference Pub Date : 2012-06-04 DOI: 10.1109/IITC.2012.6251566
C. Wilson, F. Lazzarino, V. Truffert, T. Kirimura, J. de Marneffe, P. Verdonck, M. Hirai, K. Nakatani, M. Tada, N. Heylen, Z. El-Mekki, K. Vanstreels, E. Van Besien, I. Ciofi, M. Stucchi, K. Croes, L. Zhang, S. Demuynck, M. Ercken, K. Xu, M. Baklanov, Z. Tokei
{"title":"Integration of a k=2.3 spin-on polymer for the sub-28nm technology node using EUV lithography","authors":"C. Wilson, F. Lazzarino, V. Truffert, T. Kirimura, J. de Marneffe, P. Verdonck, M. Hirai, K. Nakatani, M. Tada, N. Heylen, Z. El-Mekki, K. Vanstreels, E. Van Besien, I. Ciofi, M. Stucchi, K. Croes, L. Zhang, S. Demuynck, M. Ercken, K. Xu, M. Baklanov, Z. Tokei","doi":"10.1109/IITC.2012.6251566","DOIUrl":"https://doi.org/10.1109/IITC.2012.6251566","url":null,"abstract":"In this work we integrate an advanced k=2.3 spin-on polymer at 40nm ½ pitch. K-value restoration techniques are investigated and complete k-value restoration is demonstrated using an in-situ HeH2 plasma. An EUV compatible stack and a dielectric dual hard mask scheme is developed to pattern trenches with good uniformity and low litho-etch bias. The impact of scaling the dielectric spacing and of direct CMP on time dependent dielectric breakdown is also studied.","PeriodicalId":165741,"journal":{"name":"2012 IEEE International Interconnect Technology Conference","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114208887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Computational analysis of mechanical and electromigration reliability problems 机械和电迁移可靠性问题的计算分析
2012 IEEE International Interconnect Technology Conference Pub Date : 2012-06-04 DOI: 10.1109/IITC.2012.6251575
I. Avci, P. Balasingam, V. Chawla, K. El-Sayed, M. Johnson, A. Kucherov, S. Li, B. Mishra, Y. Oh, B. Polsky, Z. Qin, S. Simeonov, S. Tian, X. Xu, W. Zhou, M. Zhu
{"title":"Computational analysis of mechanical and electromigration reliability problems","authors":"I. Avci, P. Balasingam, V. Chawla, K. El-Sayed, M. Johnson, A. Kucherov, S. Li, B. Mishra, Y. Oh, B. Polsky, Z. Qin, S. Simeonov, S. Tian, X. Xu, W. Zhou, M. Zhu","doi":"10.1109/IITC.2012.6251575","DOIUrl":"https://doi.org/10.1109/IITC.2012.6251575","url":null,"abstract":"The reliability of complex interconnect structures at all levels of the chip integration hierarchy has become a major concern due to the use of fine feature sizes, diverse materials, and complex 3D architectures. Reliability issues range from stress related failures such as dielectric cracking and interface debonding during manufacturing to electrical and mechanical failures such as electromigration and void formation during operation. This paper summarizes computational results obtained using a unified physics-based 3D simulation framework.","PeriodicalId":165741,"journal":{"name":"2012 IEEE International Interconnect Technology Conference","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122973203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Development of highly reliable Cu wiring of L/S=1/1µm for chip to chip interconnection 开发高可靠的L/S=1/1µm铜布线，用于芯片间互连
2012 IEEE International Interconnect Technology Conference Pub Date : 2012-06-04 DOI: 10.1109/IITC.2012.6251635
T. Kanki, J. Ikeda, Y. Kobayashi, S. Suda, Y. Nakata, T. Nakamura
{"title":"Development of highly reliable Cu wiring of L/S=1/1µm for chip to chip interconnection","authors":"T. Kanki, J. Ikeda, Y. Kobayashi, S. Suda, Y. Nakata, T. Nakamura","doi":"10.1109/IITC.2012.6251635","DOIUrl":"https://doi.org/10.1109/IITC.2012.6251635","url":null,"abstract":"Highly dense and reliable Cu wiring of L/S=1/1μm for chip to chip interconnection was developed, by improving the semi-additive process To meet the reliability requirements, a mechanism for leakage failures in the HAST environment was identified, and the improved processes for suppressing Cu corrosion and diffusion were established by reducing halogen ions and covering with metal cap barriers.","PeriodicalId":165741,"journal":{"name":"2012 IEEE International Interconnect Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129711613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Post Porosity Plasma Protection applied to a wide range of ultra low-k materials 后孔隙等离子体保护适用于各种超低k材料
2012 IEEE International Interconnect Technology Conference Pub Date : 2012-06-04 DOI: 10.1109/IITC.2012.6251565
T. Frot, W. Volksen, T. Magbitang, L. Krupp, P. Rice, S. Purushothaman, M. Lofaro, S. Cohen, R. Bruce, G. Dubois
{"title":"Post Porosity Plasma Protection applied to a wide range of ultra low-k materials","authors":"T. Frot, W. Volksen, T. Magbitang, L. Krupp, P. Rice, S. Purushothaman, M. Lofaro, S. Cohen, R. Bruce, G. Dubois","doi":"10.1109/IITC.2012.6251565","DOIUrl":"https://doi.org/10.1109/IITC.2012.6251565","url":null,"abstract":"Integration challenges of porous ultra low-k (ULK) materials resulting from the ULKs' high sensitivity to process damage constitute a major roadblock to their implementation in back-end-of-the-line wiring structures for advanced technology nodes. The Post Porosity Plasma Protection strategy, which we introduced last year, enables to shield the ULKs' porosity during key integration steps. We report here on the feasibility of the protection across a wider range of dielectric constants and the advantages offered by our strategy during integration in terms of critical dimension integrity and electrical properties.","PeriodicalId":165741,"journal":{"name":"2012 IEEE International Interconnect Technology Conference","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120953514","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
3D TSV and interposer 3D TSV和中介器
2012 IEEE International Interconnect Technology Conference Pub Date : 2012-06-01 DOI: 10.1109/IITC.2012.6251585
J. W. Fraunhofer
{"title":"3D TSV and interposer","authors":"J. W. Fraunhofer","doi":"10.1109/IITC.2012.6251585","DOIUrl":"https://doi.org/10.1109/IITC.2012.6251585","url":null,"abstract":"3D System Integration is one of the most significant strategic key technologies in the field of microelectronic packaging and System integration. Besides the progress in silicon technology following “Moore's law” there is an increasing demand for highly miniaturized complex system architectures which are based on 3D SiPs. Currently different approaches are in development, which will result in complex 3D stacking approaches using TSV technology. Silicon interposer with TSV are one important element to combine different advanced devices into one miniaturized system with high functionality. The main target today is to achieve cost reduction in TSV processing and stack assembly. But nevertheless 3D WL approaches technology is one of the main technology drivers in packaging and system integration. The presentation will highlight same major aspects and current status of this technology.","PeriodicalId":165741,"journal":{"name":"2012 IEEE International Interconnect Technology Conference","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131804304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Nanophotonic interconnection networks for performance-energy optimized computing 用于性能-能量优化计算的纳米光子互连网络
2012 IEEE International Interconnect Technology Conference Pub Date : 2011-06-26 DOI: 10.1109/ICTON.2011.5970765
K. Bergman
{"title":"Nanophotonic interconnection networks for performance-energy optimized computing","authors":"K. Bergman","doi":"10.1109/ICTON.2011.5970765","DOIUrl":"https://doi.org/10.1109/ICTON.2011.5970765","url":null,"abstract":"As computing performance continues to grow through the increasing number of processing cores, the interconnection network has become the central subsystem for providing the communications infrastructure. Electronic interconnects are increasingly bound by the associated power dissipation of high-bandwidth data movement. Recent advances in chip-scale silicon photonic technologies have created the potential for developing optical interconnects that can offer highly energy efficient communications. This talk will examine the design and performance of photonic networks-on-chip architectures that support both on-chip and memory access communication in an energy efficient manner.","PeriodicalId":165741,"journal":{"name":"2012 IEEE International Interconnect Technology Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122819577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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