Novel Cu reflow seed process for Cu/low-k 64nm pitch dual damascene interconnects and beyond

Abstract

A novel Cu reflow seed process which utilizes PVD technology components has been demonstrated for 64nm pitch dual damascene interconnects. Prior to Cu electroplating, small features can be partially filled with Cu by this newly developed Cu reflow seed process. More than 60% improvement of via-chain yield is obtained by Cu reflow seed compared to conventional seed. A sacrificial Cu underlayer was applied to reduce barrier damage effects during Cu reflow seed processing, successfully suppressing any line resistance increase. This Cu reflow seed process is a promising candidate for improving Cu fill properties of 64nm pitch interconnects and beyond.