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2012 IEEE International Interconnect Technology Conference最新文献

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Compact modeling and performance optimization of 3D chip-to-chip interconnects with transmission lines, vias and discontinuities 紧凑的建模和性能优化的3D芯片对芯片互连与传输线，过孔和不连续
2012 IEEE International Interconnect Technology Conference Pub Date : 2012-06-04 DOI: 10.1109/IITC.2012.6251646
V. Kumar, R. Sharma, Jikai Chen, A. Kapoor, R. Bashirullah, P. Kohl, A. Naeemi
{"title":"Compact modeling and performance optimization of 3D chip-to-chip interconnects with transmission lines, vias and discontinuities","authors":"V. Kumar, R. Sharma, Jikai Chen, A. Kapoor, R. Bashirullah, P. Kohl, A. Naeemi","doi":"10.1109/IITC.2012.6251646","DOIUrl":"https://doi.org/10.1109/IITC.2012.6251646","url":null,"abstract":"In this paper we present a compact model for analysis of 3D chip-to-chip interconnect pathways consisting of planar transmission lines, vias, package and pin discontinuities. The model accurately captures signal losses for a wide frequency spectrum with very small error when compared with HSPICE circuit simulations. The interconnect pathway is optimized for maximum bandwidth density and minimum energy-per-bit highlighting the performance improvement obtained using low-k, air-clad planar interconnects over conventional substrate materials.","PeriodicalId":165741,"journal":{"name":"2012 IEEE International Interconnect Technology Conference","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131808637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Phase Change Memories challenges: A material and process perspective 相变存储器的挑战:材料和工艺的视角
2012 IEEE International Interconnect Technology Conference Pub Date : 2012-06-04 DOI: 10.1109/IITC.2012.6251591
S. Maitrejean, G. Ghezzi, E. Gourvest, G. Beneventi, A. Fantini, N. Pashkov, G. Navarro, A. Roule, F. Fillot, P. Noé, S. Lhostis, O. Cueto, C. Jahan, J. Nodin, A. Persico, M. Armand, L. Dussault, C. Valle, P. Michallon, R. Morel, A. Brenac, M. Audier, J. Raty, F. Hippert, L. Perniola, V. Sousa, B. De Salvo
{"title":"Phase Change Memories challenges: A material and process perspective","authors":"S. Maitrejean, G. Ghezzi, E. Gourvest, G. Beneventi, A. Fantini, N. Pashkov, G. Navarro, A. Roule, F. Fillot, P. Noé, S. Lhostis, O. Cueto, C. Jahan, J. Nodin, A. Persico, M. Armand, L. Dussault, C. Valle, P. Michallon, R. Morel, A. Brenac, M. Audier, J. Raty, F. Hippert, L. Perniola, V. Sousa, B. De Salvo","doi":"10.1109/IITC.2012.6251591","DOIUrl":"https://doi.org/10.1109/IITC.2012.6251591","url":null,"abstract":"Among all the new memories concepts, Phase Change Memories (PCM) is one of the most promising. However, various challenges remain. This paper reviews the materials and processes required to face these challenges. As an example, attention will be made on the effect of Phase change material composition on stability of the amorphous phase i.e. on the retention of the information. Additionally, it is showed how specific processes such as CVD or ALD can be developed in order to minimize the current required to amorphize the phase change material i.e. to reset the device. Finally, with the perspectives of the advanced integration nodes, experimental results on the effect of scaling on phase transformation are presented and discussed.","PeriodicalId":165741,"journal":{"name":"2012 IEEE International Interconnect Technology Conference","volume":"427 2‐3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132704380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Cu-Cu hybrid bonding as option for 3D IC stacking Cu-Cu杂化键合作为3D IC堆叠的选项
2012 IEEE International Interconnect Technology Conference Pub Date : 2012-06-04 DOI: 10.1109/IITC.2012.6251571
Y. H. Hu, C. S. Liu, M. Lii, K. Rebibis, A. Jourdain, A. la Manna, E. Beyne, C. H. Yu
{"title":"Cu-Cu hybrid bonding as option for 3D IC stacking","authors":"Y. H. Hu, C. S. Liu, M. Lii, K. Rebibis, A. Jourdain, A. la Manna, E. Beyne, C. H. Yu","doi":"10.1109/IITC.2012.6251571","DOIUrl":"https://doi.org/10.1109/IITC.2012.6251571","url":null,"abstract":"Cu-Cu bonding is seen as possible option to enable 3D-IC integration within a reasonable cost. In case of 3D stacking, the TSVs can be revealed (nails) at wafer back side and bonded directly on a Cu landing pad. This can offer small pitch IOs and save the cost of extra processing like RDL (Re-Distribution Layer) and bumping. In this work we present the results achieved by developing the process for TSV nail reveal in order to enable electrical yielding Cu-Cu thermal compression bonding (TCB). Thus, we have investigated the impact on different TSV nail structures under various TCB conditions for a minimum TSV pitch of 10 μm. Three different TSV nail structures have been defined: No Nail exposed, Flat Surface of TSV, and Dome Shape of TSV (refer to fig 1). TSVs with different height (2um and 5um) are also been generated in case of dome shape. We initially report the results achieved on the different structures in case of different bonding conditions. Later we focus on the best performing structures and demonstrate that the use of an underfill (UF) is necessary to ensure good adhesion between dies.","PeriodicalId":165741,"journal":{"name":"2012 IEEE International Interconnect Technology Conference","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116741511","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Comparison of x-ray diffraction, wafer curvature and Raman spectroscopy to evaluate the stress evolution in Copper TSV's 比较x射线衍射，晶圆曲率和拉曼光谱来评价铜TSV的应力演化
2012 IEEE International Interconnect Technology Conference Pub Date : 2012-06-04 DOI: 10.1109/IITC.2012.6251639
C. Wilson, I. De Wolf, B. Vandevelde, J. De Messemaeker, J. Ablett, A. Redolfi, V. Simons, E. Beyne, K. Croes
{"title":"Comparison of x-ray diffraction, wafer curvature and Raman spectroscopy to evaluate the stress evolution in Copper TSV's","authors":"C. Wilson, I. De Wolf, B. Vandevelde, J. De Messemaeker, J. Ablett, A. Redolfi, V. Simons, E. Beyne, K. Croes","doi":"10.1109/IITC.2012.6251639","DOIUrl":"https://doi.org/10.1109/IITC.2012.6251639","url":null,"abstract":"In this work we compare techniques to measure the stress in Cu through silicon via's (TSV's) and study the stress as a function of post-plating anneal time and temperature. Our results show that each technique was able to measure the stresses with good agreement. However, wafer curvature was limited to measuring the in-plane stress and the top down Raman spectroscopy geometry is dominated by the out-of-plane stress. Only x-ray diffraction could measure all principal stress components, showing high in-plane stress for longer post-plating anneals that could affect transistor performance.","PeriodicalId":165741,"journal":{"name":"2012 IEEE International Interconnect Technology Conference","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132431577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Novel seed layer formation using direct electroless copper deposition on ALD-Ru layer for high aspect ratio TSV 采用直接化学镀铜在ALD-Ru层上制备高纵横比TSV的新型种层
2012 IEEE International Interconnect Technology Conference Pub Date : 2012-06-04 DOI: 10.1109/IITC.2012.6251660
F. Inoue, H. Philipsen, A. Radisic, S. Armini, Y. Civale, P. Leunissen, S. Shingubara
{"title":"Novel seed layer formation using direct electroless copper deposition on ALD-Ru layer for high aspect ratio TSV","authors":"F. Inoue, H. Philipsen, A. Radisic, S. Armini, Y. Civale, P. Leunissen, S. Shingubara","doi":"10.1109/IITC.2012.6251660","DOIUrl":"https://doi.org/10.1109/IITC.2012.6251660","url":null,"abstract":"High aspect ratio through-Si vias (2 μmφ, AR 15) have been filled without voids on coupon scale by using an electroless deposited Cu seed layer on ALD-Ru. The total Cu overburden, which is ELD and filling Cu, was about 700 nm. In addition, the electroless Cu bath showed good stability during 2 hours with controlling pH to stabilize the deposition process. These results show the feasibility of electroless deposition in TSV processing.","PeriodicalId":165741,"journal":{"name":"2012 IEEE International Interconnect Technology Conference","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121803184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Demonstration of an electrically functional 34 nm metal pitch interconnect in ultralow-k ILD using spacer-based pitch quartering 在超低k ILD中使用间隔基间距四分化的电功能34 nm金属间距互连的演示
2012 IEEE International Interconnect Technology Conference Pub Date : 2012-06-04 DOI: 10.1109/IITC.2012.6251665
M. van Veenhuizen, G. Allen, M. Harmes, T. Indukuri, C. Jezewski, B. Krist, H. Lang, A. Myers, R. Schenker, K. Singh, R. Turkot, H. Yoo
{"title":"Demonstration of an electrically functional 34 nm metal pitch interconnect in ultralow-k ILD using spacer-based pitch quartering","authors":"M. van Veenhuizen, G. Allen, M. Harmes, T. Indukuri, C. Jezewski, B. Krist, H. Lang, A. Myers, R. Schenker, K. Singh, R. Turkot, H. Yoo","doi":"10.1109/IITC.2012.6251665","DOIUrl":"https://doi.org/10.1109/IITC.2012.6251665","url":null,"abstract":"The patterning of a 34 nm metal pitch interconnect was realized using a spacer-based pitch quartering scheme. The pattern is transferred into an ultralow-k ILD using a process that avoids ILD buckling and structure collapse. Resulting features were metallized with copper, and electrically characterized. Measurement results show expected trends with drawn dimensions.","PeriodicalId":165741,"journal":{"name":"2012 IEEE International Interconnect Technology Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123981930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Novel flowable CVD process technology for sub-20nm interlayer dielectrics 亚20nm层间介质的新型流动CVD工艺技术
2012 IEEE International Interconnect Technology Conference Pub Date : 2012-06-04 DOI: 10.1109/IITC.2012.6251590
Honggun Kim, Seungheon Lee, Jun-Won Lee, B. Bae, Y. Choi, Y. Koh, H. Yi, Eunkee Hong, M. Kang, S. Nam, Ho-Kyu Kang, C. Chung, Jinhyung Park, N.M. Cho, Seungmoo Lee
{"title":"Novel flowable CVD process technology for sub-20nm interlayer dielectrics","authors":"Honggun Kim, Seungheon Lee, Jun-Won Lee, B. Bae, Y. Choi, Y. Koh, H. Yi, Eunkee Hong, M. Kang, S. Nam, Ho-Kyu Kang, C. Chung, Jinhyung Park, N.M. Cho, Seungmoo Lee","doi":"10.1109/IITC.2012.6251590","DOIUrl":"https://doi.org/10.1109/IITC.2012.6251590","url":null,"abstract":"Flowable CVD (Chemical Vapor Deposition) process having merits in terms of both superior gap-fill performance of SOD (Spin-on Dielectric) and process stability of CVD was introduced for the interlayer dielectric (ILD) in sub-20nm devices based on new concept and precursor. Remote plasma during low temperature deposition and ozone treatment was adopted to stabilize the film. We also developed a novel Flowable CVD process which does not oxidize Si or electrode, resulted in removal of Si3N4 stopper layer as an oxidation or diffusion barrier. After the application of Flowable CVD to 20nm DRAM ILD, we could reduce not only loading capacitance of Bit-line by 15% but also enhance comparable productivity. Through the successful development of sub-20nm DRAM ILD Gap-fill process, Flowable CVD was successful demonstrated as a promising candidate for mass production-worthy ILD in sub-20nm next generation devices.","PeriodicalId":165741,"journal":{"name":"2012 IEEE International Interconnect Technology Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129924561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Ultra-high density 3D SRAM cell designs for monolithic 3D integration 用于单片3D集成的超高密度3D SRAM单元设计
2012 IEEE International Interconnect Technology Conference Pub Date : 2012-06-04 DOI: 10.1109/IITC.2012.6251581
Chang Liu, S. Lim
{"title":"Ultra-high density 3D SRAM cell designs for monolithic 3D integration","authors":"Chang Liu, S. Lim","doi":"10.1109/IITC.2012.6251581","DOIUrl":"https://doi.org/10.1109/IITC.2012.6251581","url":null,"abstract":"This paper presents design options for 3D SRAM cells to enable ultra-high density 3D SRAM based on monolithic 3D integration. Our target technology offers one tier of NMOS devices, another for PMOS devices, and nano-scale inter-tier vias. Choosing the most compact 22nm 2D SRAM as our design baseline, we first achieve a 33% footprint area reduction by simply splitting the NMOS and PMOS devices in the 2D cell into two tiers. We then explore several alternative design options that fully take the advantage of monolithic 3D technology under area and reliability goals. Our options include (1) the conventional 2P4N cell with new sizing, (2) 3P3N cell with voltage enhancement, (3) 4P4N 8T cell. We achieve 44% and 45% area reduction with the first two and 40% with the last, all under high static noise margin, data retention voltage, and write margin under both nominal and statistical conditions.","PeriodicalId":165741,"journal":{"name":"2012 IEEE International Interconnect Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129761921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 33
Circuit-technology co-optimization of heterogeneous hierarchical network-on-chips 异构分层片上网络的电路技术协同优化
2012 IEEE International Interconnect Technology Conference Pub Date : 2012-06-04 DOI: 10.1109/IITC.2012.6251645
N. Kani, A. Naeemi
{"title":"Circuit-technology co-optimization of heterogeneous hierarchical network-on-chips","authors":"N. Kani, A. Naeemi","doi":"10.1109/IITC.2012.6251645","DOIUrl":"https://doi.org/10.1109/IITC.2012.6251645","url":null,"abstract":"Because of the ever increasing number of cores present on a single chip, fast and energy efficient, inter-core data communication has become a major concern. Various network-on-chip (NoC) topologies and flow controls have been presented in literature. In this paper, for the first time, the benefits of a hierarchical heterogeneous NoC are quantized using a comprehensive circuit-interconnect technology co-optimization. It is demonstrated that this optimal hybrid network provides lower end-to-end latency and power consumption compared to other homogeneous solutions. It is shown that not only is there a significant decrease in latency and power, but also the hardware overhead and wiring area in such a system are significantly reduced.","PeriodicalId":165741,"journal":{"name":"2012 IEEE International Interconnect Technology Conference","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121400140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Annealing process and structural considerations in controlling extrusion-type defects Cu TSV 控制Cu TSV挤压型缺陷的退火工艺和结构考虑
2012 IEEE International Interconnect Technology Conference Pub Date : 2012-06-04 DOI: 10.1109/IITC.2012.6251586
J. An, K. Moon, Soyoung Lee, Do-Sun Lee, Kiyoung Yun, Byung-lyul Park, Hojoon Lee, Jiwoong Sue, Yeong L. Park, Gilheyun Choi, Ho-Kyu Kang, C. Chung
{"title":"Annealing process and structural considerations in controlling extrusion-type defects Cu TSV","authors":"J. An, K. Moon, Soyoung Lee, Do-Sun Lee, Kiyoung Yun, Byung-lyul Park, Hojoon Lee, Jiwoong Sue, Yeong L. Park, Gilheyun Choi, Ho-Kyu Kang, C. Chung","doi":"10.1109/IITC.2012.6251586","DOIUrl":"https://doi.org/10.1109/IITC.2012.6251586","url":null,"abstract":"Stresses induced by the large volume of Cu in Through Silicon Vias (TSV) can result in global/local Cu extrusion which may affect reliability in 3D chip stacking technologies beyond the 28 nm node for high performance mobile devices. In this work, TSV structural factors that can influence extrusion post via filling are studied. In addition, the impact of the electroplating chemistry and annealing schemes on local extrusion type defect formation in TSVs are also studied.","PeriodicalId":165741,"journal":{"name":"2012 IEEE International Interconnect Technology Conference","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132518446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
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