Compact modeling and performance optimization of 3D chip-to-chip interconnects with transmission lines, vias and discontinuities

Abstract

In this paper we present a compact model for analysis of 3D chip-to-chip interconnect pathways consisting of planar transmission lines, vias, package and pin discontinuities. The model accurately captures signal losses for a wide frequency spectrum with very small error when compared with HSPICE circuit simulations. The interconnect pathway is optimized for maximum bandwidth density and minimum energy-per-bit highlighting the performance improvement obtained using low-k, air-clad planar interconnects over conventional substrate materials.