Ultra-high density 3D SRAM cell designs for monolithic 3D integration

Abstract

This paper presents design options for 3D SRAM cells to enable ultra-high density 3D SRAM based on monolithic 3D integration. Our target technology offers one tier of NMOS devices, another for PMOS devices, and nano-scale inter-tier vias. Choosing the most compact 22nm 2D SRAM as our design baseline, we first achieve a 33% footprint area reduction by simply splitting the NMOS and PMOS devices in the 2D cell into two tiers. We then explore several alternative design options that fully take the advantage of monolithic 3D technology under area and reliability goals. Our options include (1) the conventional 2P4N cell with new sizing, (2) 3P3N cell with voltage enhancement, (3) 4P4N 8T cell. We achieve 44% and 45% area reduction with the first two and 40% with the last, all under high static noise margin, data retention voltage, and write margin under both nominal and statistical conditions.