C. Wilson, I. De Wolf, B. Vandevelde, J. De Messemaeker, J. Ablett, A. Redolfi, V. Simons, E. Beyne, K. Croes
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引用次数: 7
Abstract
In this work we compare techniques to measure the stress in Cu through silicon via's (TSV's) and study the stress as a function of post-plating anneal time and temperature. Our results show that each technique was able to measure the stresses with good agreement. However, wafer curvature was limited to measuring the in-plane stress and the top down Raman spectroscopy geometry is dominated by the out-of-plane stress. Only x-ray diffraction could measure all principal stress components, showing high in-plane stress for longer post-plating anneals that could affect transistor performance.