2012 IEEE International Interconnect Technology Conference最新文献_第3页

BEOL challenges for 14nm node and beyond 14nm及以上节点的BEOL挑战

2012 IEEE International Interconnect Technology Conference Pub Date : 2012-06-04 DOI: 10.1109/IITC.2012.6251662

B. Taylor, Xuan Lin, Xunyuan Zhang, Hoon Kim, M. He, V. Ryan

引用次数: 1

Impact of advanced patterning options, 193nm and EUV, on local interconnect performance 先进的模式选项，193nm和EUV，对本地互连性能的影响

2012 IEEE International Interconnect Technology Conference Pub Date : 2012-06-04 DOI: 10.1109/IITC.2012.6251594

M. Stucchi, Z. Tokei, S. Demuynck, Y. Siew

引用次数: 7

Measurement and analysis of thermal stresses in 3-D integrated structures containing through-silicon-vias 含硅通孔三维集成结构的热应力测量与分析

2012 IEEE International Interconnect Technology Conference Pub Date : 2012-06-04 DOI: 10.1109/IITC.2012.6251570

Tengfei Jiang, Suk-kyu Ryu, Qiu Zhao, J. Im, H.-Y Son, Kwang-yoo Byun, Rui Huang, P. Ho

引用次数: 9

An experimental study on the TSV reliability: Electromigration (EM) and time dependant dielectric breakdown (TDDB) TSV可靠性的实验研究:电迁移(EM)和时间相关介质击穿(TDDB)

2012 IEEE International Interconnect Technology Conference Pub Date : 2012-06-04 DOI: 10.1109/IITC.2012.6251574

Hyuniun Choi, S. Choi, M. Yeo, Sung-Dong Cho, Dong-Cheon Baek, Jongwoo Park

引用次数: 15

Effect of thermal cycling on the signal integrity and morphology of TSV isolation liner- SiO2 热循环对TSV隔离衬里- SiO2信号完整性和形貌的影响

2012 IEEE International Interconnect Technology Conference Pub Date : 2012-06-04 DOI: 10.1109/IITC.2012.6251582

C. Okoro, Y. Obeng

引用次数: 7

A fully integrated novel Wafer-Level LED package (WL2P) technology for extremely low-cost solid state lighting devices 一种完全集成的新型晶圆级LED封装(WL2P)技术，用于极低成本的固态照明设备

2012 IEEE International Interconnect Technology Conference Pub Date : 2012-06-04 DOI: 10.1109/IITC.2012.6251634

A. Kojima, M. Shimada, Y. Akimoto, M. Shimojuku, H. Furuyama, S. Obata, K. Higuchi, Y. Sugizaki, H. Shibata

{"title":"A fully integrated novel Wafer-Level LED package (WL2P) technology for extremely low-cost solid state lighting devices","authors":"A. Kojima, M. Shimada, Y. Akimoto, M. Shimojuku, H. Furuyama, S. Obata, K. Higuchi, Y. Sugizaki, H. Shibata","doi":"10.1109/IITC.2012.6251634","DOIUrl":"https://doi.org/10.1109/IITC.2012.6251634","url":null,"abstract":"Reduction of cost has become the most important challenge for solid state lighting. We proposed a novel Wafer-Level LED Packaging (WL2P) technology, which enables both extremely low cost and small size for future solid state lighting. Where a conventional package needs individual assembly steps, resulting in high fabrication cost, we carried out from growth of the GaN layer, over formation of Inter Layer Dielectric (ILD), wiring for solder pad to printing the phosphor layer on a whole wafer in our WL2P. Thus, for the first time a fully integrated wafer-level process was successfully applied to light emitting diode (LED) devices. It was clearly demonstrated that our WL2P has an excellent thermal resistance as low as 24.2K/W in the 0.6×0.3mm size prototype structure because of the direct connection of Cu wiring to the light emitting layer and a maximum injection power density was as high as 1157W/cm2 in a difference of 50°C between junction temperature and ambient temperature on the aluminum based printed wiring board (PCB)","PeriodicalId":165741,"journal":{"name":"2012 IEEE International Interconnect Technology Conference","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115702463","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Ultrafine pitch (6-µm) evolution of Cu-Cu bonded interconnects in 3D wafer-on-wafer stacking 三维片对片堆叠中Cu-Cu键合互连的超细间距(6µm)演变

2012 IEEE International Interconnect Technology Conference Pub Date : 2012-06-04 DOI: 10.1109/IITC.2012.6251659

L. Peng, J. Fan, L. Zhang, H. Li, D. F. Lim, C. Tan

引用次数: 8

In-situ metal/dielectric capping process for electromigration enhancement in Cu interconnects 原位金属/介质封盖工艺增强铜互连中的电迁移

2012 IEEE International Interconnect Technology Conference Pub Date : 2012-06-04 DOI: 10.1109/IITC.2012.6251568

C. Yang, F. Chen, B. Li, H. Shobha, S. Nguyen, A. Grill, W. Ye, J. Aubuchon, M. Shek, D. Edelstein

引用次数: 2

Thermo-mechanical and electrical characterization of through-silicon vias with a vapor deposited polyimide dielectric liner 气相沉积聚酰亚胺介电衬里的硅通孔的热机械和电学特性

2012 IEEE International Interconnect Technology Conference Pub Date : 2012-06-04 DOI: 10.1109/IITC.2012.6251638

B. Sapp, R. Quon, C. O’Connell, R. Geer, K. Maekawa, K. Sugita, H. Hashimoto, A. Gracias, I. Ali

{"title":"Thermo-mechanical and electrical characterization of through-silicon vias with a vapor deposited polyimide dielectric liner","authors":"B. Sapp, R. Quon, C. O’Connell, R. Geer, K. Maekawa, K. Sugita, H. Hashimoto, A. Gracias, I. Ali","doi":"10.1109/IITC.2012.6251638","DOIUrl":"https://doi.org/10.1109/IITC.2012.6251638","url":null,"abstract":"A study using a vapor deposited polyimide (VDP) dielectric liner to electrically isolate through-silicon vias (TSVs) has demonstrated electrical and thermo-mechanical performance superior to sub-atmospheric chemically vapor deposited (SACVD) tetraethyl orthosilicate (TEOS) liner in 5 μm × 50 μm TSVs. The VDP liner is continuous and highly conformal, with a worst-case coverage of 85% relative to the target deposition thickness. Moreover, the material integrates through TSV metallization, anneal, and polish. Electrically, VDP provides lower inter-via capacitance than the more conventional SACVD TEOS liner. Mechanically, blanket film stress of VDP measured as a function of temperature shows no hysteresis up to 400°C and a stress delta during cycling of only 45 MPa. The delta is an order of magnitude lower than SACVD TEOS. The thermo-mechanical behavior of VDP also results in a lower residual stress in the silicon area surrounding the structure, which enables a smaller keep-away zone for TSVs and effectively increases the density of transistors in silicon for 3D integrated systems.","PeriodicalId":165741,"journal":{"name":"2012 IEEE International Interconnect Technology Conference","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126745431","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Integration of a low-k organic polymer material (k=2.3) for reducing both resistance and capacitance 集成低k有机聚合物材料(k=2.3)，降低电阻和电容

2012 IEEE International Interconnect Technology Conference Pub Date : 2012-06-04 DOI: 10.1109/IITC.2012.6251579

M. Hirai, Y. Akiyama, K. Koga, H. Kawakami, K. Nakatani, M. Tada

引用次数: 0