{"title":"A new procedure to extract ultra-low specific contact resistivity","authors":"Hsuan-Tzu Tseng, B. Tsui","doi":"10.1109/IITC.2012.6251584","DOIUrl":"https://doi.org/10.1109/IITC.2012.6251584","url":null,"abstract":"In this work, a new procedure to extract ultra-low specific contact resistivity down to 10-9 Ω-cm2 is proposed. Design guidelines of the test structure are analyzed with 3-D simulation. Compared to the typical Cross-bridge-Kelvin resistor structure, the proposed structure has much better accuracy at low resistivity regime, looser design rules, simpler fabrication process.","PeriodicalId":165741,"journal":{"name":"2012 IEEE International Interconnect Technology Conference","volume":"3 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124295005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Y. Kimura, A. Kobayashi, D. Ishikawa, A. Nakano, K. Matsushita, N. Kobayashi
{"title":"Plasma enhanced ALD pore sealing for highly porous SiOCH films with k = 2.0","authors":"Y. Kimura, A. Kobayashi, D. Ishikawa, A. Nakano, K. Matsushita, N. Kobayashi","doi":"10.1109/IITC.2012.6251572","DOIUrl":"https://doi.org/10.1109/IITC.2012.6251572","url":null,"abstract":"In order to implement highly porous PECVD SiOCH films with k = 2.0 in ILD integration, the UV-assisted restoration to remove plasma damages related with dry etch and pore sealing by plasma enhanced ALD (PEALD)-SiN formation to prevent the metal penetration into the film during subsequent metallization process was investigated. Sequential application of the restoration and pore sealing processes was proved to be the best solution enabling successful sealing capability with preserving pristine k-value of the porous SiOCH films.","PeriodicalId":165741,"journal":{"name":"2012 IEEE International Interconnect Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129240441","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"High-efficient and high-accurate chip to wafer bonding for size-free MEMS-IC integration by using fine patterned self-assembled monolayer","authors":"Jian Lu, Y. Nakano, H. Takagi, R. Maeda","doi":"10.1109/IITC.2012.6251580","DOIUrl":"https://doi.org/10.1109/IITC.2012.6251580","url":null,"abstract":"A hydrophobic self-assembled monolayer (SAM) was applied for high-efficient chip to wafer self-alignment and bonding with reasonable high alignment speed (in millisecond) and high accuracy (≤ 1μm). Hydrophilic frame at the edge of each binding-site was demonstrated effective for a successful self-alignment, while superfine pattern at the center was used to control the bonding strength. The effects of Au/Cr wire were also studied to extend above approach for various MEMS-IC integration processes.","PeriodicalId":165741,"journal":{"name":"2012 IEEE International Interconnect Technology Conference","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132590074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Hsu, R. P. Huang, W. Lin, C. Huang, Y. Hsieh, W. Tsao, C. H. Chen, Y. M. Lin, T. Hung, H. Hsu, C. H. Wang, J. Y. Wu
{"title":"Micro-scratch reduction of replacement metal gate aluminum chemical mechanical polishing at 28nm technology node","authors":"C. Hsu, R. P. Huang, W. Lin, C. Huang, Y. Hsieh, W. Tsao, C. H. Chen, Y. M. Lin, T. Hung, H. Hsu, C. H. Wang, J. Y. Wu","doi":"10.1109/IITC.2012.6251583","DOIUrl":"https://doi.org/10.1109/IITC.2012.6251583","url":null,"abstract":"The defectivity control of replacement metal gate (RMG) chemical mechanical polishing was important for high-k metal gate (HKMG) process. Micro-scratches of RMG CMP easily caused shorting or open of devices. In this study, the micro-scratch reduction of aluminum chemical mechanical polishing (AlCMP) has been investigated to provide solutions for preventing the formation of micro-scratches. Micro-scratches can be reduced by implementing soft pads at platen 2 and platen 3, pad cleaning chemical, and optimized post cleaning condition. Soft pads can reduce micro-scratch levels of AlCMP process, especially at platen 2. However, AlCMP with soft pads easily suffer serious dishing or erosion. Therefore, the balance between micro-scratches and dishing or erosion was crucial for pad selection of AlCMP. Besides, removal of pad stain was also important. Pad stain removed by pad cleaning chemical could get a lower micro-scratch level of AlCMP. In addition to polishing process, post cleaning process was a source of micro-scratch for AlCMP. An unsuitable post cleaning condition caused a counter effect of micro-scratch reduction.","PeriodicalId":165741,"journal":{"name":"2012 IEEE International Interconnect Technology Conference","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115739987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
N. Inoue, M. Tagami, F. Ito, H. Yamamoto, J. Kawahara, E. Soda, H. Shobha, S. Gates, S. Cohen, E. Liniger, A. Madan, J. Protzman, E. T. Ryan, V. Ryan, M. Ueki, Y. Hayashi, T. Spooner
{"title":"Robust low-k film with sub-nm pores and high carbon content for highly reliable Cu/low-k BEOL modules","authors":"N. Inoue, M. Tagami, F. Ito, H. Yamamoto, J. Kawahara, E. Soda, H. Shobha, S. Gates, S. Cohen, E. Liniger, A. Madan, J. Protzman, E. T. Ryan, V. Ryan, M. Ueki, Y. Hayashi, T. Spooner","doi":"10.1109/IITC.2012.6251641","DOIUrl":"https://doi.org/10.1109/IITC.2012.6251641","url":null,"abstract":"Critical parameters of low-k films were defined to keep capacitance benefit and TDDB reliability in the scaling BEOL module, according to various analyses. In order to meet the criteria of high carbon content, low porosity with small pores, and high adhesion strength with less adhesion layer, precursor and process were designed for the SiOCH with k~2.5. The benefits in integration and reliability from the newly developed robust low-k film were verified through the trench-first integration of 80 nm-pitch BEOL modules.","PeriodicalId":165741,"journal":{"name":"2012 IEEE International Interconnect Technology Conference","volume":"348 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115886535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Y. Barbarin, L. Zhao, P. Verdonck, M. Baklanov, K. Croes, Z. Tokei
{"title":"Time dependent dielectric breakdown study of organo silicate glass materials over a wide range of k-values","authors":"Y. Barbarin, L. Zhao, P. Verdonck, M. Baklanov, K. Croes, Z. Tokei","doi":"10.1109/IITC.2012.6251576","DOIUrl":"https://doi.org/10.1109/IITC.2012.6251576","url":null,"abstract":"The time dependent dielectric breakdown (TDDB) of four organo-silicate-glass (OSG) films with varying porosity (k=2.0, 2.5, 2.8 & 3.0) was investigated using metal-insulator-semiconductor (MIS) capacitors. Without any barrier, the dielectrics show lower TDDB-lifetimes under Cu ion drift conditions, where the OSG-2.8-film exhibits a better performance. Other results are that the damage caused by TaN/Ta barriers doesn't significantly change the TDDB performance and that the OSG-2.0-film showed excellent TDDB lifetimes.","PeriodicalId":165741,"journal":{"name":"2012 IEEE International Interconnect Technology Conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123225702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
L. Cao, K. Ganesh, L. Zhang, O. Aubel, C. Hennesthal, E. Zschech, P. Ferreira, P. Ho
{"title":"Analysis of grain structure by precession electron diffraction and effects on electromigration reliability of Cu interconnects","authors":"L. Cao, K. Ganesh, L. Zhang, O. Aubel, C. Hennesthal, E. Zschech, P. Ferreira, P. Ho","doi":"10.1109/IITC.2012.6251667","DOIUrl":"https://doi.org/10.1109/IITC.2012.6251667","url":null,"abstract":"In this paper, a recently developed high resolution electron diffraction technique is employed to characterize the grain orientation and grain boundaries for 45 nm node Cu interconnects with SiCN capping. The results are applied to evaluate the grain structure effect on electromigration (EM) reliability. We first calculate the flux divergence for void formation using interfacial and grain boundary diffusivities extracted from the resistance evolution of test structures observed during EM tests. To further correlate grain structure statistics with EM failure statistics, the EM lifetime distribution for Cu interconnects with CoWP capping is analyzed using a microstructure-based statistical model.","PeriodicalId":165741,"journal":{"name":"2012 IEEE International Interconnect Technology Conference","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125427648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Engineering the extendibility of Cu/low-k BEOL technology","authors":"D. Edelstein","doi":"10.1109/IITC.2012.6251651","DOIUrl":"https://doi.org/10.1109/IITC.2012.6251651","url":null,"abstract":"Copper dual damascene BEOL technology has been in production now for 14 years and 7 CMOS generations, since it shipped in its first chips in late 1997, and was first ramped to high volume production in mid-1998. Besides benefits in performance and manufacturability, perhaps the main benefit has been to keep the door open for continued Moore's Law scaling of on-chip wiring, where Al(Cu)-based wires could not have extended - either for fine line current densities and reliability, or multilevel hierarchical scaling for large/thick lines to help circumvent the RC scaling crisis.","PeriodicalId":165741,"journal":{"name":"2012 IEEE International Interconnect Technology Conference","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124586819","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jonggi Kim, I. Mok, Sunghoon Lee, Kyumin Lee, H. Sohn
{"title":"RESET-first Resistance Switching Mechanism of HfO2 films with Ti electrode","authors":"Jonggi Kim, I. Mok, Sunghoon Lee, Kyumin Lee, H. Sohn","doi":"10.1109/IITC.2012.6251589","DOIUrl":"https://doi.org/10.1109/IITC.2012.6251589","url":null,"abstract":"RESET-first resistive switching mechanism in HfO<sub>2-x</sub> with Ti electrode was studied. RESET resistive switching was observed in annealed Ti/HfO<sub>2</sub> film. The redox phenomenon from Ti/HfO<sub>2</sub> to TiO<sub>x</sub>/HfO<sub>2-x</sub> was investigated with high angle annular dark field-scanning transmission electron microscopy, EDX, and x-ray photoelectron spectroscopy. Analysis shows that redox reaction from Ti/HfO<sub>2</sub> to TiOx/HfO<sub>2-x</sub> was responsible for an increase of initial current with increasing the post-annealing temperature and the migration of oxygen ions at interface region under external electrical bias was contributed to bipolar resistive switching behavior.","PeriodicalId":165741,"journal":{"name":"2012 IEEE International Interconnect Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130552398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"It's about the power: An architect's view of interconnect","authors":"B. Dally","doi":"10.1109/IITC.2012.6251592","DOIUrl":"https://doi.org/10.1109/IITC.2012.6251592","url":null,"abstract":"Summary form only given. As integrated circuit technology scales chips are becoming power, not area limited, and the power dissipated moving bits on, off, and across chips is becoming increasingly important. This talk gives an architect's perspective on future chip interconnect. The demand for interconnect is driven by the application. Both SoCs and high-performance processors have demanding interconnect requirements. In modern chips, these requirements are met by organizing global interconnect as a network-on-chip or NoC. The regularity afforded by this organization enables layout and circuit optimizations. To reduce the energy per bit-mm, low-energy signaling with sophisticated circuits are becoming more widely used. It is important to optimize the entire interconnect system - the wire, the circuit, and the NoC together - not just each of the three in isolation.","PeriodicalId":165741,"journal":{"name":"2012 IEEE International Interconnect Technology Conference","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133896707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}