Circuit-technology co-optimization of heterogeneous hierarchical network-on-chips

Abstract

Because of the ever increasing number of cores present on a single chip, fast and energy efficient, inter-core data communication has become a major concern. Various network-on-chip (NoC) topologies and flow controls have been presented in literature. In this paper, for the first time, the benefits of a hierarchical heterogeneous NoC are quantized using a comprehensive circuit-interconnect technology co-optimization. It is demonstrated that this optimal hybrid network provides lower end-to-end latency and power consumption compared to other homogeneous solutions. It is shown that not only is there a significant decrease in latency and power, but also the hardware overhead and wiring area in such a system are significantly reduced.