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30th Annual Proceedings Reliability Physics 1992最新文献

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The evaluation of 16-Mbit memory chips with built-in reliability 具有内置可靠性的16mbit存储芯片的评估
30th Annual Proceedings Reliability Physics 1992 Pub Date : 1992-03-01 DOI: 10.1109/RELPHY.1992.187613
C. Stapper, W.A. Klaasen
{"title":"The evaluation of 16-Mbit memory chips with built-in reliability","authors":"C. Stapper, W.A. Klaasen","doi":"10.1109/RELPHY.1992.187613","DOIUrl":"https://doi.org/10.1109/RELPHY.1992.187613","url":null,"abstract":"Highly defective 16-Mb chips have been stressed under accelerated conditions to test the capability of on-chip error-correction circuits for reliability enhancement. The tradeoff between a manufacturing sort or screen yield and reliability was determined. The soft-error immunity of the trench capacitor technology in conjunction with error correction was also evaluated under accelerated conditions.<<ETX>>","PeriodicalId":154383,"journal":{"name":"30th Annual Proceedings Reliability Physics 1992","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124903161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Characterization of dynamic spatial conduction patterns on ESD protection circuitry by photon-counting imaging 用光子计数成像表征ESD保护电路的动态空间传导模式
30th Annual Proceedings Reliability Physics 1992 Pub Date : 1992-03-01 DOI: 10.1109/RELPHY.1992.187655
B. Yap, J. Jeng, L.L.S. Chang
{"title":"Characterization of dynamic spatial conduction patterns on ESD protection circuitry by photon-counting imaging","authors":"B. Yap, J. Jeng, L.L.S. Chang","doi":"10.1109/RELPHY.1992.187655","DOIUrl":"https://doi.org/10.1109/RELPHY.1992.187655","url":null,"abstract":"A photon-counting imaging method has been effectively employed to acquire the extremely weak pulse electroluminescence from a thick-field-oxide electrostatic discharge (ESD) protection device during very short pulse stressing. From this, its dynamic spatial conduction patterns with respect to different currents, pulse widths, and repetition rates could then be directly visualized and assessed. The authors have applied such an imaging method successfully in the acquisition of a full series of spatial pulsed emission patterns on circuitry during ESD simulation. This could offer a means for direct, simultaneous observation of emerging failure on such a device. The exact sequential turning-on nature of bipolar NPN snapback, on each ladder-channel and its non-uniformity in spread during different levels and widths of pulsation could also be resolved directly. The authors report on the accurate determination of the site of the resistive short on failed samples by this technique.<<ETX>>","PeriodicalId":154383,"journal":{"name":"30th Annual Proceedings Reliability Physics 1992","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128361714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Defect-free shallow P/N junction by point defect engineering 点缺陷工程的无缺陷浅P/N结
30th Annual Proceedings Reliability Physics 1992 Pub Date : 1992-03-01 DOI: 10.1109/RELPHY.1992.187631
S. Onishi, A. Ayukawa, K. Uda, K. Sakiyama
{"title":"Defect-free shallow P/N junction by point defect engineering","authors":"S. Onishi, A. Ayukawa, K. Uda, K. Sakiyama","doi":"10.1109/RELPHY.1992.187631","DOIUrl":"https://doi.org/10.1109/RELPHY.1992.187631","url":null,"abstract":"By taking advantage of high-stress SiN/sub x/ film as a source of vacancies, a defect-free shallow junction technology was developed by point defect engineering. By depositing the SiN/sub x/ film with high stress (1*10/sup 10/ dyn/cm/sup 2/) and annealing the sample, the vacancies were supplied from the SiN/sub x/-Si interface into the Si substrate to relax the stress of the SiN/sub x/ film and react with the extrinsic defect due to implantation. The density of the defects was then one order of magnitude lower than the sample without the SiN/sub x/ film. This technology is also useful for reducing the diffusion of dopant, which is controlled by the interstitial Si atoms. It was confirmed that the dopant profile of B+ was also shallower by about 10%.<<ETX>>","PeriodicalId":154383,"journal":{"name":"30th Annual Proceedings Reliability Physics 1992","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129985451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Reliability defect detection and screening during processing-theory and implementation 加工过程中的可靠性缺陷检测与筛选——理论与实现
30th Annual Proceedings Reliability Physics 1992 Pub Date : 1992-03-01 DOI: 10.1109/RELPHY.1992.187656
H. Huston, C.P. Clarke
{"title":"Reliability defect detection and screening during processing-theory and implementation","authors":"H. Huston, C.P. Clarke","doi":"10.1109/RELPHY.1992.187656","DOIUrl":"https://doi.org/10.1109/RELPHY.1992.187656","url":null,"abstract":"The authors derive a model that relates electrical in-process measurements to reliability defect occurrence. The model begins with an understanding of reliability defect physics and statistics and then uses elements of semiconductor manufacture yield modeling. An experiment, using intensive microscopic inspections, that was used to verify this model is described. The type and nature of yield and reliability defect monitors and the use of in-process electrical measurements of these monitors for reliability defect detection are described. The implementation of 'maverick' screens for a highly defective product is outlined, and the improvement in reliability that these screens provide is estimated.<<ETX>>","PeriodicalId":154383,"journal":{"name":"30th Annual Proceedings Reliability Physics 1992","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132268696","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 53
A method to project hot carrier induced punch through voltage reduction for deep submicron LDD PMOS FETs at room and elevated temperatures 一种在室温和高温下，通过压降深度亚微米LDD PMOS fet投射热载流子感应穿孔的方法
30th Annual Proceedings Reliability Physics 1992 Pub Date : 1992-03-01 DOI: 10.1109/RELPHY.1992.187637
P. Fang, J. Yue, Don Wollessen
{"title":"A method to project hot carrier induced punch through voltage reduction for deep submicron LDD PMOS FETs at room and elevated temperatures","authors":"P. Fang, J. Yue, Don Wollessen","doi":"10.1109/RELPHY.1992.187637","DOIUrl":"https://doi.org/10.1109/RELPHY.1992.187637","url":null,"abstract":"The hot-electron-induced punchthrough (HEIP) voltage (V/sub pt/) characterization technique, which can be used for half- and sub-half-micron lightly doped drain (LDD) PMOS reliability characterization, was established. It was found that, unlike other hot carrier effects, the punchthrough due to HEIP at room temperature or the temperature effects plus HEIP at higher temperatures is the most significant limitation for deep submicron LDD PMOSFETs. The high-temperature effects of V/sub pt/ were also quantified at 25 degrees C, 80 degrees C and 125 degrees C ambient temperatures. The oxide quality dependence of the HEIP was also studied.<<ETX>>","PeriodicalId":154383,"journal":{"name":"30th Annual Proceedings Reliability Physics 1992","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115286859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
New thin plastic package crack mechanism, induced by hot IC die 新的薄型塑料封装裂纹机理，由IC热模引起
30th Annual Proceedings Reliability Physics 1992 Pub Date : 1992-03-01 DOI: 10.1109/RELPHY.1992.187645
M. R. Marks
{"title":"New thin plastic package crack mechanism, induced by hot IC die","authors":"M. R. Marks","doi":"10.1109/RELPHY.1992.187645","DOIUrl":"https://doi.org/10.1109/RELPHY.1992.187645","url":null,"abstract":"Fine cracks in thin plastic packages have been observed after board tests and reliability tests with static or dynamic biasing. The new package crack mechanism was investigated and a model is proposed. Cracks in thin plastic packages can occur when the die overheats due to the latchup phenomenon in CMOS ICs. This crack mechanism is attributed to high pressure inside the package created by outgassing of plastic encapsulant material surrounding the overheated die and thermomechanical stresses. Hot-die-induced cracks are similar in appearance to moisture-induced popcorn cracks occurring during vapor-phase solder reflow. This may lead to ambiguity as to the actual cause of failure when such cracks are encountered. Non-destructive and destructive techniques are proposed to distinguish hot-die-induced cracks from popcorn cracks.<<ETX>>","PeriodicalId":154383,"journal":{"name":"30th Annual Proceedings Reliability Physics 1992","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123946699","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Using FEA to develop a MIL-HDBK-2 17 SMT model 采用有限元法建立了mil - hdbk - 217 SMT模型
30th Annual Proceedings Reliability Physics 1992 Pub Date : 1992-03-01 DOI: 10.1109/RELPHY.1992.187640
G. A. Bivens, E.F. Pello
{"title":"Using FEA to develop a MIL-HDBK-2 17 SMT model","authors":"G. A. Bivens, E.F. Pello","doi":"10.1109/RELPHY.1992.187640","DOIUrl":"https://doi.org/10.1109/RELPHY.1992.187640","url":null,"abstract":"A MIL-HDBK-217, Military Handbook for Reliability Prediction of Electronic Equipment, reliability prediction model was developed for surface mount technology (SMT) using thermal finite element analysis (FEA) simulations and environmental test data. FEAs for a number of conditions and packages were performed, the resulting strain values were translated to number of cycles to failure, and data regression distribution techniques were used to generate a failure rate model. This methodology, which is based on established analytical techniques and procedures, provides an alternative procedure for developing failure rate models when traditional approaches are not applicable.<<ETX>>","PeriodicalId":154383,"journal":{"name":"30th Annual Proceedings Reliability Physics 1992","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127401263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Mismatch drift: a reliability issue for analog MOS circuits 失配漂移:模拟MOS电路的可靠性问题
30th Annual Proceedings Reliability Physics 1992 Pub Date : 1992-03-01 DOI: 10.1109/RELPHY.1992.187627
C. Michael, H. Wang, C. Teng, J. Shibley, L. Lewicki, C. Shyu, R. Lahri
{"title":"Mismatch drift: a reliability issue for analog MOS circuits","authors":"C. Michael, H. Wang, C. Teng, J. Shibley, L. Lewicki, C. Shyu, R. Lahri","doi":"10.1109/RELPHY.1992.187627","DOIUrl":"https://doi.org/10.1109/RELPHY.1992.187627","url":null,"abstract":"Mismatch drift is a major process reliability issue for analog and mixed-signal designs. Mismatch stability was examined for a 0.8- mu m CMOS process using a cascode current minor test circuit. After 1000-h burn-in at 125 degrees C under matched gate voltage stress, no drift in parameter matching was measured. However, for the same burn-in conditions with unmatched gate voltage stress, drifts in threshold voltage mismatch of 0.3 mV for n-channel and 2.4 mV for p-channel transistor pairs have been observed. This mismatch drift is larger for short-channel devices, indicating that the drift-causing phenomenon is greater at the drain/source edge.<<ETX>>","PeriodicalId":154383,"journal":{"name":"30th Annual Proceedings Reliability Physics 1992","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125402687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Hot carrier induced HFE degradation in BiCMOS transistors 热载流子在BiCMOS晶体管中诱导HFE降解
30th Annual Proceedings Reliability Physics 1992 Pub Date : 1992-03-01 DOI: 10.1109/RELPHY.1992.187623
C.J. Varker, D. Pettengill, W. Shiau, B. Reuss
{"title":"Hot carrier induced HFE degradation in BiCMOS transistors","authors":"C.J. Varker, D. Pettengill, W. Shiau, B. Reuss","doi":"10.1109/RELPHY.1992.187623","DOIUrl":"https://doi.org/10.1109/RELPHY.1992.187623","url":null,"abstract":"Experimental results are presented of an investigation designed to develop an understanding of the physical mechanisms and the process inputs causing reduced hot carrier reliability in BiCMOS npn transistors. The overall objective is to correlate and extract information on process module and device design during product development and to develop reliability-driven rules which can be used to reduce hot carrier degradation of the forward current gain and to improve overall transistor reliability. The results show the effects of the intrinsic base implant dose and energy as well as thermal history on hot-carrier-induced forward-current-gain degradation in BiCMOS npn transistors.<<ETX>>","PeriodicalId":154383,"journal":{"name":"30th Annual Proceedings Reliability Physics 1992","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114665269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
3-dimensional simulations of temperature and current density distribution in a via structure 通孔结构中温度和电流密度分布的三维模拟
30th Annual Proceedings Reliability Physics 1992 Pub Date : 1992-03-01 DOI: 10.1109/RELPHY.1992.187670
K. Weide, W. Hasse
{"title":"3-dimensional simulations of temperature and current density distribution in a via structure","authors":"K. Weide, W. Hasse","doi":"10.1109/RELPHY.1992.187670","DOIUrl":"https://doi.org/10.1109/RELPHY.1992.187670","url":null,"abstract":"The influence of geometry (overlap, step coverage, filling ratio), and filling material on temperature and current density distributions in via structures of different forms and technologies simulated with the finite element method program ANSYS was studied. Vias of square, circular, and oval forms were investigated. The influence of via filling was observed. Reduction of current crowding and self-heating effects were found for the tungsten-filled via. Critical parameters for the filling materials were determined. Local temperature and current density distributions are shown.<<ETX>>","PeriodicalId":154383,"journal":{"name":"30th Annual Proceedings Reliability Physics 1992","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122495772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
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