{"title":"Substrate injection induced program disturb-a new reliability consideration for flash-EPROM arrays","authors":"A. Roy, R. Kazerounian, A. Kablanian, B. Eitan","doi":"10.1109/RELPHY.1992.187625","DOIUrl":"https://doi.org/10.1109/RELPHY.1992.187625","url":null,"abstract":"The development of high-density flash EPROMs is being directed towards scalability, sector erase, and 5-V-only operation. For the flash concepts that are utilizing channel hot electron injection for the programming, a new disturbance mechanism caused by substrate injection of thermally generated electrons is reported. This mechanism disturbs an erased call during programming cycles of other bits along the same bitline. The high-temperature programming requirement for flash EPROMs drastically enhances the disturbance through the strong increase in thermally generated electrons in the substrate. This program disturbance has the greatest impact on the wordline oriented sector erase memory architectures, through the increase in disturbance time.<<ETX>>","PeriodicalId":154383,"journal":{"name":"30th Annual Proceedings Reliability Physics 1992","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117073994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Internal passivation for suppression of device instabilities induced by backend processes","authors":"V. Jain, D. Pramanik, S. Nariani, C. C. Hu","doi":"10.1109/RELPHY.1992.187615","DOIUrl":"https://doi.org/10.1109/RELPHY.1992.187615","url":null,"abstract":"The concept of internal passivation has been introduced as a means of suppressing device degradation due to backend processes. The proposed concept has been demonstrated by tailoring the composition of a PECVD (plasma-enhanced chemical vapor deposition) oxide film to achieve such an internal passivation, resulting in a process with built-in reliability. Specifically, field inversion and hot carrier degradation induced by backend processing have been suppressed. The results have been duplicated on two different commercially available PECVD systems, establishing that neither the problem nor the solution was related to a specific deposition system.<<ETX>>","PeriodicalId":154383,"journal":{"name":"30th Annual Proceedings Reliability Physics 1992","volume":"129 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122830331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Role of hydrogen at poly-Si/SiO/sub 2/ interface in trap generation by substrate hot-electron injection","authors":"I. Yoshii, K. Hama, K. Hashimoto","doi":"10.1109/RELPHY.1992.187638","DOIUrl":"https://doi.org/10.1109/RELPHY.1992.187638","url":null,"abstract":"The authors investigated trap generation by substrate hot-electron injection for MOS devices in which hydrogen was intentionally incorporated by forming gas anneal. It was found that the high-temperature forming gas anneal significantly enhances both interface and oxide trap generation at oxide fields during injection above 4 MV/cm, while no enhancement has been observed below 3 MV/cm. It was also found from secondary ion mass spectroscopy (SIMS) measurements that the forming gas anneal increases the hydrogen concentration at the poly-Si/SiO/sub 2/ interface but not in the gate oxide nor at the SiO/sub 2//Si interface. Based on these experimental results, a novel trap generation model, in which hydrogen released from Si-H at the poly-Si/SiO/sub 2/ interface by hot electrons causes the enhanced trap generation, is proposed.<<ETX>>","PeriodicalId":154383,"journal":{"name":"30th Annual Proceedings Reliability Physics 1992","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126412199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Mercury porosimetry investigation of plastic, integrated circuit packages","authors":"G. Perreault, A. Thornton","doi":"10.1109/RELPHY.1992.187646","DOIUrl":"https://doi.org/10.1109/RELPHY.1992.187646","url":null,"abstract":"Mercury porosimetry was used to characterize the pores and elastic properties of plastic IC packages. Three types of pores were identified: external gaps, epoxy-metal leadframe pores, and epoxy pores. When intrusion pressure was high enough to fill all pores, porosimetry data were used to calculate elastic constants. Highly accelerated stress test (HAST) and pressure cooker test failures were analyzed the mercury porosimetry techniques. Mercury porosimetry confirmed the existence of epoxy-leadframe pores that had caused failures during HAST testing, but was not effective in detecting die passivation crack failure mechanisms.<<ETX>>","PeriodicalId":154383,"journal":{"name":"30th Annual Proceedings Reliability Physics 1992","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133815753","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Watanabe, K. Fujimoto, M. Oda, T. Nakatsuka, A. Tamura
{"title":"Rapid degradation of WSi self-aligned gate GaAs MESFET by hot carrier effect","authors":"A. Watanabe, K. Fujimoto, M. Oda, T. Nakatsuka, A. Tamura","doi":"10.1109/RELPHY.1992.187636","DOIUrl":"https://doi.org/10.1109/RELPHY.1992.187636","url":null,"abstract":"Rapid degradation of GaAs self-aligned gate MESFETs (SAGFETs) by hot carriers was observed. The degradation rate was found to depend on the type of passivation film on the GaAs surface. SAGFETs with SiN passivation were found to have higher resistance to degradation than SAGFETs with SiO/sub 2/ passivation. The results suggest that the interface between the GaAs surface and the passivation film must be considered in any model for the degradation mechanism.<<ETX>>","PeriodicalId":154383,"journal":{"name":"30th Annual Proceedings Reliability Physics 1992","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128177556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Finite element analysis of a SWEAT structure with a 3-D, nonlinear, coupled thermal-electric model","authors":"M. Dion","doi":"10.1109/RELPHY.1992.187651","DOIUrl":"https://doi.org/10.1109/RELPHY.1992.187651","url":null,"abstract":"The complexities of determining thermal characteristics within the standard wafer electromigration accelerated test (SWEAT) structure during accelerated metal integrity or electromigration tests are discussed. A 3-D, nonlinear, coupled thermal-electric finite element model is developed and was solved with the ANSYS program to investigate heat flow in several regions of the structure. The finite element model is presented. Correlation with nonlinear thermal material parameters is demonstrated, and the importance of modeling lateral heat flow in underlying oxides is shown. Extraction of thermal parameters for use in the EXTRA thermal model is discussed.<<ETX>>","PeriodicalId":154383,"journal":{"name":"30th Annual Proceedings Reliability Physics 1992","volume":"234 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114384212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Moisture sensitivity characterization of plastic surface mount devices using scanning acoustic microscopy","authors":"R. L. Shook","doi":"10.1109/RELPHY.1992.187641","DOIUrl":"https://doi.org/10.1109/RELPHY.1992.187641","url":null,"abstract":"An attempt was made to characterize the moisture ingress kinetics of six known vendor-supplied moisture-sensitive IC surface mount devices. Induced damage response by exposure to IR reflow was then characterized using C-mode scanning acoustic microscopy. Damage analysis indicated that moisture ingress sensitivity can vary significantly from device to device with little correlation to total pin count. Accelerated performance testing using temperature cycling revealed that this test is only second order effective in accelerating the failure of moisture-damaged devices. Correlation between ambient aging and accelerated testing was possible using both an established failure criteria assessment and moisture diffusion calculations. Safe ambient exposure times from out-of-the-dry-bag to board assembly for these devices were determined using this methodology.<<ETX>>","PeriodicalId":154383,"journal":{"name":"30th Annual Proceedings Reliability Physics 1992","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114577457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A case study of two-stage fault location","authors":"P. Ryan, K. Davis, S. Rawat","doi":"10.1109/RELPHY.1992.187666","DOIUrl":"https://doi.org/10.1109/RELPHY.1992.187666","url":null,"abstract":"An industrial implementation of two-stage VLSI fault location is presented. Two-stage fault location was developed to address the size and computation time problems that were making it impractical to automate fault location with fault dictionaries. It does this by reducing the fault list and the test vector set for each faulty chip before dynamically creating a new, small fault dictionary for each diagnosis. The modern fault dictionary and the two-stage fault location technique are explained. For the case study presented, a new Intel chip was chosen. Its test set was developed and fault simulated, and it was prepared for automated fault location. Two-stage fault location was then applied to the fourteen failures available from initial product development production runs. The results are presented.<<ETX>>","PeriodicalId":154383,"journal":{"name":"30th Annual Proceedings Reliability Physics 1992","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115597403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C.T. Wang, H. Haddad, P. Berndt, B. Yeh, B. Connors
{"title":"Pipeline defects in CMOS MOSFET devices caused by SWAMI isolation","authors":"C.T. Wang, H. Haddad, P. Berndt, B. Yeh, B. Connors","doi":"10.1109/RELPHY.1992.187628","DOIUrl":"https://doi.org/10.1109/RELPHY.1992.187628","url":null,"abstract":"A pipeline defect which became a leakage path between source and drain in an n-channel MOSFET was identified. It was found that a 20-second Wright-etch will clearly delineate the pipe. The cause of the pipeline was the improper SWAMI (side wall masked isolation) etch which generated stress at the island corners. This stress generated high density dislocation lines which made vacancies readily available for enhanced phosphorus diffusion.<<ETX>>","PeriodicalId":154383,"journal":{"name":"30th Annual Proceedings Reliability Physics 1992","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125102616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Dynamic gate coupling of NMOS for efficient output ESD protection","authors":"C. Duvvury, C. Diaz","doi":"10.1109/RELPHY.1992.187639","DOIUrl":"https://doi.org/10.1109/RELPHY.1992.187639","url":null,"abstract":"A dynamic gate coupling effect that increases the electrostatic discharge (ESD) protection efficiency of NMOS output devices is reported. The authors discuss the gate coupling phenomenon for NMOS transistors and its effect under ESD transient conditions. A dynamic gate-coupled device was studied to understand the gate coupling effect. The authors present the complete phenomena and results for nonsilicided devices as well as for silicided structures. The measured ESD stress results are given. The gate coupling effect and device operation under ESD are explained by using modeling and simulation results. The design issues for optimum output ESD protection are also discussed.<<ETX>>","PeriodicalId":154383,"journal":{"name":"30th Annual Proceedings Reliability Physics 1992","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117054421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}