Dynamic gate coupling of NMOS for efficient output ESD protection

Abstract

A dynamic gate coupling effect that increases the electrostatic discharge (ESD) protection efficiency of NMOS output devices is reported. The authors discuss the gate coupling phenomenon for NMOS transistors and its effect under ESD transient conditions. A dynamic gate-coupled device was studied to understand the gate coupling effect. The authors present the complete phenomena and results for nonsilicided devices as well as for silicided structures. The measured ESD stress results are given. The gate coupling effect and device operation under ESD are explained by using modeling and simulation results. The design issues for optimum output ESD protection are also discussed.<>