A method to project hot carrier induced punch through voltage reduction for deep submicron LDD PMOS FETs at room and elevated temperatures

Abstract

The hot-electron-induced punchthrough (HEIP) voltage (V/sub pt/) characterization technique, which can be used for half- and sub-half-micron lightly doped drain (LDD) PMOS reliability characterization, was established. It was found that, unlike other hot carrier effects, the punchthrough due to HEIP at room temperature or the temperature effects plus HEIP at higher temperatures is the most significant limitation for deep submicron LDD PMOSFETs. The high-temperature effects of V/sub pt/ were also quantified at 25 degrees C, 80 degrees C and 125 degrees C ambient temperatures. The oxide quality dependence of the HEIP was also studied.<>