C. Michael, H. Wang, C. Teng, J. Shibley, L. Lewicki, C. Shyu, R. Lahri
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引用次数: 16
摘要
失配漂移是模拟和混合信号设计过程可靠性的主要问题。采用级联码电流小测试电路对0.8 μ m CMOS工艺的失配稳定性进行了测试。在匹配的栅极电压应力下,125℃下1000 h的老化后,参数匹配无漂移。然而,在栅极电压应力不匹配的情况下,观察到n沟道晶体管对阈值电压失配漂移为0.3 mV, p沟道晶体管对阈值电压失配漂移为2.4 mV。对于短通道器件,这种不匹配漂移更大,表明在漏极/源极边缘引起漂移的现象更大。
Mismatch drift: a reliability issue for analog MOS circuits
Mismatch drift is a major process reliability issue for analog and mixed-signal designs. Mismatch stability was examined for a 0.8- mu m CMOS process using a cascode current minor test circuit. After 1000-h burn-in at 125 degrees C under matched gate voltage stress, no drift in parameter matching was measured. However, for the same burn-in conditions with unmatched gate voltage stress, drifts in threshold voltage mismatch of 0.3 mV for n-channel and 2.4 mV for p-channel transistor pairs have been observed. This mismatch drift is larger for short-channel devices, indicating that the drift-causing phenomenon is greater at the drain/source edge.<>