2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)最新文献

{"title":"High temperature endurable hermetic sealing material selection and reliability comparison for IR gas sensor module packaging","authors":"K. Y. Au, D. Zhi, V. Chidambaram, Bu Lin, Kropelnicki Piotr, Chuan KaiLiang","doi":"10.1109/EPTC.2016.7861430","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861430","url":null,"abstract":"Infrared (IR) sensor module deploy for hazardous gas leakage detection is crucial to provide and maintain offshore Oil & Gas platform asset integrity and improve operational risk management by avoiding accidental disaster and mitigating risk associated with danger involve in oil production. These sensor modules must remain robust under harsh ambient environment. Hence, designing novel high temperature interconnects material bill of materials (BOM) with compatible barrier metallization [1-2] and robust hermetic sealing material further enhanced sensor reliability. By reducing BOM oxidation degradation at high ambient temperature [3-4], reliability of the sensor is maintained. For this study, the TV (test vehicle, Figure 1) consist of an Alumina (Al2O3) substrate casing which houses all the active components and is hermetically sealed with a Silicon (Si) die that acts as an IR filter. Laser and seam welding are common method of performing hermetic sealing but they suffer from low throughput issues. An investigative benchmark of various hermetic sealing methods and materials will be discussed in great details, targeting Alumina (Al2O3) to Silicon (Si) interfaces sealing. Both sealing surfaces have no metallization. Materials such as high temperature low outgassing adhesive, glass frit paste and ceramic paste will be applied on the TV via dispensing or screen printing method and their corresponding hermeticity performance of the sealing interface will be investigated. The silicon filter is 3.7 × 3.7 mm in size and will be mounted on a 3.8 × 3.8mm ceramic substrate casing. TV hermeticity degradation response (base on MIL-STD-883J Method 1014.14 which requires 10−9 cc/sec leak rate) is examined after reliability evaluation is conducted, which include Thermal Cycling (TC, −55°C to 250°C, 500 cycles) and High Temperature Storage (HTS, 250°C, 500 hours). The objective of this paper is to report the high temperature reliability performance of various benchmarked sealing materials and understand and document the degradation mechanism and hermeticity response (via MIL-STD leak test) after HTS and TC test at 250°C.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131092155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Void risk prediction for semiconductor packages considering the air venting analysis with fluid/structure interaction method","authors":"Chih-Chung Hsu, Chao-Tsai Huang, R. Chang","doi":"10.1109/EPTC.2016.7861468","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861468","url":null,"abstract":"According as high density packaging options such as multi-die staking or package stacking technologies are developed, the major mold process related quality concerns such as severe air void entrapment under the die. The accurate analysis of venting is important for realistic prediction of voids that may occur during chip encapsulation. This study reports a perspective investigation of computational modeling of air venting analysis with fluid-structure interaction (FSI) during microchip encapsulation process. The venting analysis is to calculate the pressure drop of the air that passes through the vent and include the effects of air pressure on the flow front. Through the integrated method with FSI method, we can predict precisely the FSI behavior with the dynamic mesh deformation technique simultaneously in accordance with venting analysis. This is different from previous study that only one way considered fixed geometry during venting analysis. Furthermore, a series of analyses are conducted to compare the experimental data to study the void risk. This result shows that the proposed modeling methodology is able to obtain better match of the experiment vs. simulation data than a traditional analysis.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"1997 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132491479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"TAIKO wafer ball attach","authors":"S. Schröder, Markus Schröder, W. Reinert, K. H. Priewasser","doi":"10.1109/EPTC.2016.7861519","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861519","url":null,"abstract":"Ball attach on ultra-thin 200 mm TAIKO wafers is considered a challenge but it can be mastered. The TAIKO wafer grinding concept is based on the thinning of an inner area of a silicon wafer leaving an outer ring as stiffening frame for wafer handling without an additional carrier [1]. The process development methodology for a near industrial TAIKO wafer balling pilot line is described. A phased process development methodology was applied with different residual wafer thicknesses, wafer ball diameters and balling pitches to check yield affecting topics and process throughput.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"04 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128860909","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"On-demand laser-sintering of copper micro-particles on ferrite/epoxy resin substrates for power electronics devices","authors":"H. Sonoda, R. Atsumi, M. Mita, K. Yamasaki, K. Maekawa","doi":"10.1109/EPTC.2016.7861494","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861494","url":null,"abstract":"Thick copper wiring on ferrite/epoxy resin substrate was carried out by laser sintering of the paste prepared with 1 μm-diameter copper micro-particles and organic solvents. A 532 nm-wavelength Nd:YVO4 green laser has a high adsorption both to the copper micro-particle paste and to the ferrite/epoxy resin substrate are used for laser ablation of the substrate and laser sintering. From the microscopic observations and property evaluations of the laser-processed ferrite/epoxy resin substrate with copper, the following conclusions are obtained: (1) The paste prepared with 1 μm-diameter copper and organic solvents made it possible a small-volume dispensing as well as a good laser sintering; (2) The use of 532 nm-wavelength Nd:YVO4 green laser has a high adsorption both to the copper micro-particle paste and to the ferrite/epoxy resin substrate, resulting in the formation of the laser-sintered film with 20 μm in thickness and 15 μΩ·cm in specific resistance. No damage to the substrate occurred; (3) The adhesion between the sintered film and the substrate is attributed to the removal of the surface epoxy layer by laser ablation. Copper micro-particles penetrate to the exposed ferrite particles, being mechanically locked with each other at the interface; (4) The scratch test with a cotton swab and the peel test with an adhesion tape show that no separation took place at the interface.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126613535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Large format packaging — An alternative format for discrete packaging: Its challenges and solutions","authors":"E. Kuah, J. Hao, W. Chan, Wu Kai, C. Ashokkumar, S. Ho, L. Christie, John Macleod","doi":"10.1109/EPTC.2016.7861513","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861513","url":null,"abstract":"This paper will review the challenges on large format encapsulation with respect to mold cap thickness control, encapsulant impact on moldability such as flow mark and flow mark on final product. Control of mold co-planarity is best performed dynamically during molding, otherwise it would be challenging to obtain good co-planarity within ± 20 μm. Moldability demand such encapsulant coverage with highly viscous material, flow-ability and flow mark are discussed. Warpage control heavily depends on the formulation of the encapsulant and the form of encapsulant, i.e., granular, liquid and sheet.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121487487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Board level reliability of automotive eWLB (embedded wafer level BGA) FOWLP","authors":"Lin Yaojian, Bernard Adams., R. Antonicelli, L. Petit, D. Yap, K. Wong, S. Yoon","doi":"10.1109/EPTC.2016.7861518","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861518","url":null,"abstract":"With shrinking chip sizes, Wafer Level Packaging (WLP) is becoming an attractive packaging technology with many advantages in comparison to standard Ball Grid Array (BGA) packages. With the advancement of various fan-out Wafer Level Packaging (FOWLP) designs, this advanced technology has proven to be a more optimal and promising solution compared to fan-in WLP because of the greater design flexibility in having more input/output (I/O) and improved thermal performance. In addition, FOWLP shows superior high-frequency performance with its shorter and simpler interconnection compared to flip chip packaging. eWLB (embedded wafer level BGA) is a type of FOWLP that enables applications requiring smaller form factor, excellent heat dissipation and thin package profiles. It also has the potential to evolve into various configurations with proven yields and manufacturing experience based on over 8 years of high volume production. This paper discusses the recent advancements in robust board level reliability performance of eWLB for automotive applications. A Design of Experiment (DOE) study will be reviewed which demonstrates improved Temperature Cycle on Board (TCoB) performance with experimental results. Several DOE studies were planned and test vehicles were prepared with the variables of solder materials, solder mask opening/Cu pad size of redistribution layer (RDL) design, copper (Cu) RDL thickness and under bump metallurgy (UBM), and Cu pad design (NSMD, SMD) on a printed circuit board (PCB). With these parametric studies and TCoB reliability tests, the test vehicle passed 1000x temperature cycles (TC). Daisy chain test vehicles were used for TCoB reliability performance in industry standard test conditions.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122799429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Within-feature-shape (WiF) control of mega pillars for high density fan-out (HDFO) technology","authors":"B. Buckalew, T. Ponnuswamy, S. Mayer, K. Thorkelsson, J. Oberst, G. Graham","doi":"10.1109/EPTC.2016.7861592","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861592","url":null,"abstract":"IC packaging technology has evolved in a quite diverse manner over the past decade, addressing both high-end and low-end applications, resulting in approaches such as package-on-package (PoP), fan-out wafer-level package (FOWLP), 3D IC integration with through-silicon via (TSV), and 2.5D with TSV-Si interposer. FOWLP technology offers significant cost and performance advantages relative to other packaging approaches and is, therefore, receiving widespread adoption throughout the industry for applications such as smartphone/tablet application processor (AP), baseband (BB) module, field-programmable gate array (FPGA), graphics processing unit (GPU), etc. As a result, FOWLP technology is expected to ramp at a strong growth rate over the immediate future [1]. FOWLP technology comprises conventional under-bump metallization (UBM) and pillar/micro-pillar, as well as new routing/connection applications such as fine line redistribution layer (RDL) (sub 5×5 μm), integrated via-RDL structures and mega pillars (>150 μm) [2]. These new applications drive fundamental challenges in electrodeposition. For instance, the mega pillars consist of 180–220 μm (200 μm average) copper thickness while standard copper pillar applications typically vary between 20 and 40 μm (30 μm average) thickness. This large disparity in thickness can translate to approximately 6x plating times if a similar deposition rate was to be used. Furthermore, some integration requirements for mega pillars warrant extremely high within-die uniformities and flat bump shape. Attaining such high quality plating performance can greatly minimize the need for downstream grinding requirements. This paper will focus on the advancement of copper electrodeposition for mega pillars.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114133656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Alternative dicing solution of Multi-Project Wafer (MPW) by Stealth Dicing","authors":"Jen-Hsien Chang, Pei-Ling Chen, Chien-Chih Huang, Guo-Hao Cao, Ji-Ye Wang","doi":"10.1109/EPTC.2016.7861488","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861488","url":null,"abstract":"Multi-Project Wafer (MPW) is designed for cost saving and fast prototype but conventional Blade Dicing process is time consuming and high risk to cause die loss because repetitive Blade Dicing process. Stealth Dicing is an alternative solution of Blade Dicing, patterned by Hamamatsu Photonics, which has potential for MPW dicing solution. This paper presents first successful MPW dicing by Stealth Dicing instead of Blade Dicing which FT (Functional Test) yield has been proved. In this study, the team evaluated the process of MPW dicing by Stealth Dicing. During the evaluation, some phenomenon has been observed which damage MPW chips. This study has clarified the phenomenon and found solution for the damage. After solving the problem, the result shows that yield of Stealth Dicing and Blade Dicing are comparable and Stealth Dicing is able to be used on MPW.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114842855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Low stress dielectric layers for wafer level packages to reduce wafer warpage and improve board-level temperature-cycle reliability","authors":"J. Huneke, SweeTeck Tay","doi":"10.1109/EPTC.2016.7861466","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861466","url":null,"abstract":"This paper presents a negative-tone photoimageable spinon dielectric material that is based on a unique molecule for wafer level packaging application. The molecule is an extended polyimide having photoactive maleimide end groups. It is an ideal alternative to conventional dielectric materials for solving both the wafer warpage and temperature cycle RDL crack issues.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"219 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116069488","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Antenna array integrated on multilayer organic package for millimeter-wave applications","authors":"Cheng-Yu Ho, Ming-Fong Jhong, Po-Chih Pan, Chen-Chao Wang, Chun-Yen Ting, Ken-Huang, L. Hsueh, Shang-Hao Liu, Hung-chia Chang","doi":"10.1109/EPTC.2016.7861559","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861559","url":null,"abstract":"A high-directivity microstrip-fed Yagi-Uda antenna has been developed for millimeter-wave applications. This work proposed antenna is built on a low-cost and low-loss multilayer organic substrate for flip chip ball grid array (FCBGA) package. The proposed antenna achieves both broadband and high gain characteristics, which meets the requirement of IEEE 802.1 lad standard. The four-element Yagi-Uda array is also implemented to low-cost and low-loss multilayer organic substrate. The four-element design results in a peak gain of 12–14.5 dBi at operating frequency band. The proposed antenna shows excellent performance in free space and is suitable for millimeter-wave application, such as smart phone, laptops, and wireless router for point-to-point communication systems.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123836106","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}