2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)最新文献

{"title":"High temperature endurable hermetic sealing material selection and reliability comparison for IR gas sensor module packaging","authors":"K. Y. Au, D. Zhi, V. Chidambaram, Bu Lin, Kropelnicki Piotr, Chuan KaiLiang","doi":"10.1109/EPTC.2016.7861430","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861430","url":null,"abstract":"Infrared (IR) sensor module deploy for hazardous gas leakage detection is crucial to provide and maintain offshore Oil & Gas platform asset integrity and improve operational risk management by avoiding accidental disaster and mitigating risk associated with danger involve in oil production. These sensor modules must remain robust under harsh ambient environment. Hence, designing novel high temperature interconnects material bill of materials (BOM) with compatible barrier metallization [1-2] and robust hermetic sealing material further enhanced sensor reliability. By reducing BOM oxidation degradation at high ambient temperature [3-4], reliability of the sensor is maintained. For this study, the TV (test vehicle, Figure 1) consist of an Alumina (Al2O3) substrate casing which houses all the active components and is hermetically sealed with a Silicon (Si) die that acts as an IR filter. Laser and seam welding are common method of performing hermetic sealing but they suffer from low throughput issues. An investigative benchmark of various hermetic sealing methods and materials will be discussed in great details, targeting Alumina (Al2O3) to Silicon (Si) interfaces sealing. Both sealing surfaces have no metallization. Materials such as high temperature low outgassing adhesive, glass frit paste and ceramic paste will be applied on the TV via dispensing or screen printing method and their corresponding hermeticity performance of the sealing interface will be investigated. The silicon filter is 3.7 × 3.7 mm in size and will be mounted on a 3.8 × 3.8mm ceramic substrate casing. TV hermeticity degradation response (base on MIL-STD-883J Method 1014.14 which requires 10−9 cc/sec leak rate) is examined after reliability evaluation is conducted, which include Thermal Cycling (TC, −55°C to 250°C, 500 cycles) and High Temperature Storage (HTS, 250°C, 500 hours). The objective of this paper is to report the high temperature reliability performance of various benchmarked sealing materials and understand and document the degradation mechanism and hermeticity response (via MIL-STD leak test) after HTS and TC test at 250°C.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131092155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Void risk prediction for semiconductor packages considering the air venting analysis with fluid/structure interaction method","authors":"Chih-Chung Hsu, Chao-Tsai Huang, R. Chang","doi":"10.1109/EPTC.2016.7861468","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861468","url":null,"abstract":"According as high density packaging options such as multi-die staking or package stacking technologies are developed, the major mold process related quality concerns such as severe air void entrapment under the die. The accurate analysis of venting is important for realistic prediction of voids that may occur during chip encapsulation. This study reports a perspective investigation of computational modeling of air venting analysis with fluid-structure interaction (FSI) during microchip encapsulation process. The venting analysis is to calculate the pressure drop of the air that passes through the vent and include the effects of air pressure on the flow front. Through the integrated method with FSI method, we can predict precisely the FSI behavior with the dynamic mesh deformation technique simultaneously in accordance with venting analysis. This is different from previous study that only one way considered fixed geometry during venting analysis. Furthermore, a series of analyses are conducted to compare the experimental data to study the void risk. This result shows that the proposed modeling methodology is able to obtain better match of the experiment vs. simulation data than a traditional analysis.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"1997 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132491479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"TAIKO wafer ball attach","authors":"S. Schröder, Markus Schröder, W. Reinert, K. H. Priewasser","doi":"10.1109/EPTC.2016.7861519","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861519","url":null,"abstract":"Ball attach on ultra-thin 200 mm TAIKO wafers is considered a challenge but it can be mastered. The TAIKO wafer grinding concept is based on the thinning of an inner area of a silicon wafer leaving an outer ring as stiffening frame for wafer handling without an additional carrier [1]. The process development methodology for a near industrial TAIKO wafer balling pilot line is described. A phased process development methodology was applied with different residual wafer thicknesses, wafer ball diameters and balling pitches to check yield affecting topics and process throughput.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"04 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128860909","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"On-demand laser-sintering of copper micro-particles on ferrite/epoxy resin substrates for power electronics devices","authors":"H. Sonoda, R. Atsumi, M. Mita, K. Yamasaki, K. Maekawa","doi":"10.1109/EPTC.2016.7861494","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861494","url":null,"abstract":"Thick copper wiring on ferrite/epoxy resin substrate was carried out by laser sintering of the paste prepared with 1 μm-diameter copper micro-particles and organic solvents. A 532 nm-wavelength Nd:YVO4 green laser has a high adsorption both to the copper micro-particle paste and to the ferrite/epoxy resin substrate are used for laser ablation of the substrate and laser sintering. From the microscopic observations and property evaluations of the laser-processed ferrite/epoxy resin substrate with copper, the following conclusions are obtained: (1) The paste prepared with 1 μm-diameter copper and organic solvents made it possible a small-volume dispensing as well as a good laser sintering; (2) The use of 532 nm-wavelength Nd:YVO4 green laser has a high adsorption both to the copper micro-particle paste and to the ferrite/epoxy resin substrate, resulting in the formation of the laser-sintered film with 20 μm in thickness and 15 μΩ·cm in specific resistance. No damage to the substrate occurred; (3) The adhesion between the sintered film and the substrate is attributed to the removal of the surface epoxy layer by laser ablation. Copper micro-particles penetrate to the exposed ferrite particles, being mechanically locked with each other at the interface; (4) The scratch test with a cotton swab and the peel test with an adhesion tape show that no separation took place at the interface.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126613535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Large format packaging — An alternative format for discrete packaging: Its challenges and solutions","authors":"E. Kuah, J. Hao, W. Chan, Wu Kai, C. Ashokkumar, S. Ho, L. Christie, John Macleod","doi":"10.1109/EPTC.2016.7861513","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861513","url":null,"abstract":"This paper will review the challenges on large format encapsulation with respect to mold cap thickness control, encapsulant impact on moldability such as flow mark and flow mark on final product. Control of mold co-planarity is best performed dynamically during molding, otherwise it would be challenging to obtain good co-planarity within ± 20 μm. Moldability demand such encapsulant coverage with highly viscous material, flow-ability and flow mark are discussed. Warpage control heavily depends on the formulation of the encapsulant and the form of encapsulant, i.e., granular, liquid and sheet.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121487487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Board level reliability of automotive eWLB (embedded wafer level BGA) FOWLP","authors":"Lin Yaojian, Bernard Adams., R. Antonicelli, L. Petit, D. Yap, K. Wong, S. Yoon","doi":"10.1109/EPTC.2016.7861518","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861518","url":null,"abstract":"With shrinking chip sizes, Wafer Level Packaging (WLP) is becoming an attractive packaging technology with many advantages in comparison to standard Ball Grid Array (BGA) packages. With the advancement of various fan-out Wafer Level Packaging (FOWLP) designs, this advanced technology has proven to be a more optimal and promising solution compared to fan-in WLP because of the greater design flexibility in having more input/output (I/O) and improved thermal performance. In addition, FOWLP shows superior high-frequency performance with its shorter and simpler interconnection compared to flip chip packaging. eWLB (embedded wafer level BGA) is a type of FOWLP that enables applications requiring smaller form factor, excellent heat dissipation and thin package profiles. It also has the potential to evolve into various configurations with proven yields and manufacturing experience based on over 8 years of high volume production. This paper discusses the recent advancements in robust board level reliability performance of eWLB for automotive applications. A Design of Experiment (DOE) study will be reviewed which demonstrates improved Temperature Cycle on Board (TCoB) performance with experimental results. Several DOE studies were planned and test vehicles were prepared with the variables of solder materials, solder mask opening/Cu pad size of redistribution layer (RDL) design, copper (Cu) RDL thickness and under bump metallurgy (UBM), and Cu pad design (NSMD, SMD) on a printed circuit board (PCB). With these parametric studies and TCoB reliability tests, the test vehicle passed 1000x temperature cycles (TC). Daisy chain test vehicles were used for TCoB reliability performance in industry standard test conditions.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122799429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Investigation of residual stress effect during the anodic bonding process with different bondable materials for wafer level packaging design","authors":"Xiaodong Hu, Maozhou Meng, Manuel Baeuscher, U. Hansen, S. Maus, O. Gyenge, P. Mackowiak, B. Mukhopadhyay, N. Vokmer, O. Ehrmann, Klaus Dieter Lang, H. Ngo","doi":"10.1109/EPTC.2016.7861498","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861498","url":null,"abstract":"The anodic bonding technology is a well-established industrial technique, which has been reported to account for the mainstream packaging methods in Micro-Electro-Mechanical-Systems (MEMS) devices, such as hermetic sealing, encapsulation, and wafer level packaging. It is widely recognized that the CTEs of many bondable materials are temperature dependent. The residual stress is induced between the bonding interface during the cooling process. This residual stress degrades the device's performance, e.g. its offset, linearity, sensitivity or dynamic behavior. Currently, the mainstream methods for improving anodic bonding performance focus on reducing the bonding temperature, using a thinner glass layer, or using materials with optimized CTE (similar to silicon over a wide temperature range) to reduce the residual stress. As we understand[1], decreasing the bonding temperature reduces the bond quality. In this work, the residual stress is investigated by using the classical lamination theory (CLT) and experiments. The experimental observation showed a good agreement with the CLT calculation method. The study illustrates an efficient methodology to estimate the residual stress in an anodically bonded pair which leads to some suggestions to optimize the design of wafer level packaging.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125582665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Copper circuit traces by laser cladding with powder injection for additive manufactured mechatronic devices","authors":"M. Mueller, O. Hentschel, M. Schmidt, J. Franke","doi":"10.1109/EPTC.2016.7861551","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861551","url":null,"abstract":"Laser cladding allows for a fast, flexible and direct plotting of electric conductive structures on polymer based substrates. The surface of the substrate is selectively melted by a focused laser beam. Simultaneously, a metal powder is lead through a powder nozzle. This nozzle is oriented laterally or coaxially to the laser beam. As a result, a molten bath of substrate and powder material is created. After cooling and solidification a welding bead on the substrate surface is formed. With this generation of circuit traces mechatronic devices can be built up, especially for high current power electronic applications. In this paper copper circuit traces on polymere substrates, produced by laser cladding with powder injection are characterized for their optical, electrical and mechanical properties by measuring resistance, adhesive strengths and current-carrying capacity including the effects of simulated environmental influences.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125232243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Novel WLCSP technology solution for fusion device of CMOS integrated circuit with MEMS","authors":"T. Murayama, T. Sakuishi, Y. Morikawa","doi":"10.1109/EPTC.2016.7861541","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861541","url":null,"abstract":"For the realization of the IoT (Internet of Things) society where the arrival is strongly predicted soon, the construction of an intelligent sensor network is important. For such a sensor network construction, the enormous numerical fusion devices that CMOS devices and MEMS sensors are integrated are essential. To develop WLCSP (Wafer Level Chip Size Packaging) technologies as high density packaging technology for mass production of the high reliability and low-cost devices, improving performance and downsizing of these devices, is important including novel process integration. Considering new integration of WLCSP in future, it is considered necessary to develop DRIE (Deep Reactive Ion Etching) technology for etching Si, mold, metal and insulator, or heterogeneous sacks of these materials. We have developed Non-Bosch “scallop-free” etching method for Si DRIE in our original high density NLD (magnetic Neutral Loop Discharge) plasma. [1] In this work, the first trial of Bosch etching was conducted using same plasma source of Non-Bosch. It is quietly important to control atmosphere of the sealed cavity with MEMS, there is a possibility that higher-quality controlling technology for atmosphere of sealed cavity is required with WLCSP evolution in future. Conventional MEMS etching method is Bosch etching. In Bosch method, Si is etched to anisotropic profile by using fluorine radical reaction to Si, and sidewall passivation of fluorocarbon polymer. [2] Due to such etch reaction mechanism, the residues of fluorine and fluorocarbon exist on etched surface, it is possible that these residual will have a negative impact to the cavity atmosphere after sealed. In this paper, as a part of the data acquisition to consider about the management standard of the sealed cavity atmosphere, we started comparison between Bosch and Non-Bosch to investigate whether influence of Si etching method influence to sealed cavity atmosphere or not. In this work, each sample of Bosch and Non-Bosch sample was prepared using by NLD plasma etcher, then, TDS (Thermal Desorption Spectroscopy) analyses were carried out to detect desorption species from etched surface of sample. TDS analyses were conducted each process step; after Si etched, after O2 plasma ashing, and after wet cleaning for fluorocarbon polymer.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"130 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125439614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thermal management of high performance test socket for wafer level package","authors":"Yong Han, Seow Meng Low, J. Goh","doi":"10.1109/EPTC.2016.7861436","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861436","url":null,"abstract":"High performance test sockets with thermal management solutions have been developed for wafer level package of high power. Three types of active cooling solutions have been designed and integrated in the test socket. Type A of more compact size can be easily assembled in the space limited environment. Type B is much larger and more complex, including 4 direct touch copper heat pipes. Type C comprises of direct contact liquid cooler for chip heat delivery and outside exchanger for heat rejection to the environment. To maintain the maximum chip temperature under 85°C, the heating power of around 80W and 120W can be dissipated with type A and type B respectively. With Type C, the dissipated heating power can be as high as 150W. Appropriate management of test socket thermal issue will assure the success for high performance test of advanced packages.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132047885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}