2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)最新文献

{"title":"A novel trench routing for next-generation high-speed serial buses beyond 10Gbps applications","authors":"J. Kong, B. E. Cheah, K. Yong, H. Heck, L. Lo","doi":"10.1109/EPTC.2016.7861534","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861534","url":null,"abstract":"This work describes an innovative low-loss transmission line routing configuration, which enables improved channel margin in next-generation high-speed serial buses beyond 10Gbps applications. One such example is SuperSpeed Plus USB a.k.a. USB 3.1 Gen2. Ultimately, this novel routing when implemented in either substrate or printed circuit board (PCB) will extend platform length within the interconnect channel loss budget as stipulated by standard development body e.g. USB-IF specifications. This inventive routing provides huge benefit to original equipment manufacturer (OEM) in term of platform component removal (e.g. USB 3.1 re-timer that costs ∼$1) for high-speed differential links >10Gbps data transfer rates. These cost-adding repeaters would be indispensable under conventional routing for instance microstrip, stripline and dual-stripline for high-speed applications. The PCB trench routing aims to mitigate the existing and future challenges of next-gen multi-Gbps signaling, of which one of the platform length limitations is PCB interconnect loss. In this work, signaling analysis in 10Gbps USB 3.1 and 32Gbps SerDes applications have shown feasibility of yielding significant eye margin improvements i.e. up-to 30% voltage margin improvements, which also translates into ample board design flexibility with extended platform routing length.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"444 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123053828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Effects of humidity on the electro-optical-thermal characteristics of high-power LEDs","authors":"T. K. Law, Fannon Lim, Y. Li, J. Teo, S. Wei","doi":"10.1109/EPTC.2016.7861576","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861576","url":null,"abstract":"LEDs are subjected to environments with high moisture in many applications. In this paper, the experiments reveal photometric and colorimetric degradation at high humidity. Corresponding spectral power analysis and parameter extraction indicate that the flip-chip bonded LED samples show accelerated chip failure compared to the conventionally bonded samples. The chip-related failure induces greater heat accumulation, which correlates with the increase in heating power observed in the package. However, the temperature rise and thermal resistance for the flip-chip bonded LEDs do not increase substantially as compared to the conventionally bonded LEDs. This is because the junction temperature can be reduced with a flip-chip die-bonding configuration where the heat generated in the LED chip is dissipated effectively onto the AlN substrate, thereby reducing the increase in temperature rise and thermal resistance. The experimental results are supported by evaluation of the derivative structure functions. In addition, as the thermal resistance of the LED package varies with different humidity levels, there is a need to specify the conditions of humidity in data sheets as LED manufacturers routinely specify a universal thermal resistance value under a fixed operating condition.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121115669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thermal-mechanical reliability assessment of TSV structure for 3D IC integration","authors":"Huan Liu, Qinghua Zeng, Y. Guan, R. Fang, Xin Sun, F. Su, J. Chen, M. Miao, Yufeng Jin","doi":"10.1109/EPTC.2016.7861584","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861584","url":null,"abstract":"In this paper, thermal-mechanical reliability of TSV structure was investigated with thermal shock test and finite element method. The fine pitch TSV samples were subjected to thermal load, failure samples were identified by resistance measurement, the calculated characteristic life was about 340 cycles. It is revealed that thermal-mechanical stress is concentrated around TSV, the ends of TSV are susceptible to failure. FEA results indicate maximum value of maximum principal stress appears at chip area near the ends of TSV, scallop side wall induces larger shear stress than smooth side wall thus more easily leads to interfacial failure. The warpage of chips and fatigue life of solder balls under different thermal load conditions were investigated in global simulation.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127546730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Development of Chip-to-Wafer (C2W) bonding process for high density I/Os Fan-Out Wafer Level Package (FOWLP)","authors":"S. Lim, S. Chong, M. Ding, V. S. Rao","doi":"10.1109/EPTC.2016.7861516","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861516","url":null,"abstract":"In the current mobile electronics market, there is a great demand of electronics products with better performance, smaller foot print and greater package functionality with a lower manufacturing cost. Smart phones and tablets are some of the portable electronics devices that require more functions, smaller form factor and reduced power consumption requirements [1]. To address these requirements, the Multi-Chip Fan-Out Wafer Level Package (FOWLP) technology promises an alternative technology for high performance and multi-die packaging in FOWLP technology [2]. In conventional flip chip assembly, the advantages of using Cu pillar and solder micro bumps are mainly because of it allows for fine pitch applications and superior power management in terms of thermal and electrical [3]. The major difference in using copper pillar with solder micro bumps is that the solder volume are significantly reduced on each solder bump. Furthermore, the lesser solder volume on the Cu pillar bumps makes it difficult for solder self-alignment during solder reflow process [4]. Hence it is critical that good chip placement accuracy is needed in the flip-chip bonder for good solder interconnect formation especially for our work in the new RDL-first FOWLP technology with multiple die and high pin count applications [5]. In this paper, we present the chip to wafer assembly for multiple die on the RDL-First FOWLP approach. Chip-to-Wafer assembly is a promising technology for high density package application to overcome the limitation of Wafer-to-Wafer boding in terms of die stacking process yield and bonding placement accuracy on wafers. Our test vehicle is a large multi-chip package of 20×20mm2 fabricated using the RDL-First FOWLP approach. There are 2400 I/Os on the FOWLP package. The C2W flip chip process is done to attach the 3 test chips onto the 3 layers RDL film onto the 12 inch glass carrier with sacrificial layer using the mass reflow method. The assembly process was optimized and samples are built to subject to JEDEC Moisture Sensitivity Test Level 3 for reliability assessment.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124842738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Flip chip laser mark bare die strength characterization","authors":"K. Muniandy, I. Schmadlak, B. Yeung, M. Lauderdale, T. Uehling","doi":"10.1109/EPTC.2016.7861540","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861540","url":null,"abstract":"Bare die flip chip products have a high risk of die cracking as shown in Figure 1, during product electrical test or temperature cycling. The stresses experienced by the die during these events are understood. But the die strength impact after product laser marking on the die backside is not well understood. This area has a lot of room for improvement. Often, a lid is added to a flip chip package to protect the die from forces that could lead to cracking. A lid also acts as a protection to the die as it avoids the possibility to compromise the die strength by a laser mark, since the part would be marked on the lid and not on the bare die. A lid will add to product cost depending on body size. Without a data driven specification, millions of dollars could be wasted by putting a lid on a package that does not really need it. The objective of this project is to measure the die break strength as a function of laser mark profile, to optimize the laser mark across factories, and to update the maximum principal stress limit for die without a lid. Since unmarked die will always fail from the die edge due to defects introduced during singulation, it is the aim to achieve a laser marking that does not exceed this threshold in 4-point bend experiments. The laser depth measurement specification is not clearly defined, and in most cases of products, it is not even measured. A visual inspection criteria, which depicts a general outlook is used as a go-no-go. This can be used for the over-molded packages as it does not have the adverse effects as compared to marking on the bare silicon die. This study will further define the specification criteria for the laser depth control in regards to bare silicon die. Currently, all NPI's are evaluated and, if need be, mechanical simulations are done at cold temperature and under product test conditions. The study carried out was broken down to two different aspects, the first being testing the break strength and correlation of laser depth for the fully assembled package and the other using similar concept but done on singulated dies. The data collected from this study will be the input to the building of mechanical models to simulate and correlate the data. The initial results show that the different laser mark profiles creates different depth and correlates to the break strength of the die.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115021056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Laser de-bonding process development of glass substrate for Fan-out wafer level packaging","authors":"H. Hsiao, S. W. Ho, B. L. Lau","doi":"10.1109/EPTC.2016.7861439","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861439","url":null,"abstract":"Due to the demand of consumer electronics products for portable and multi-function, the development of microelectronic packaging forced to reduce the size and costs, to raise high performance. The trend causes the traditional wafer level packaging (WLP) integration great challenges: (1) when the chip size continued to scaling and solder balls became large for back-end package; it does not fit it inside the chip area for Semiconductor technological progress. (2) The chips become strong and I/O numbers increased make more difficult for WLP integration. If I/O numbers and the solder ball size decreased, it can product the I/O numbers and solder ball inside the chip area. However, the limited of the design rules for PCB assembly which has not reached manufacturing specifications for the front-end IC chips. And the I/O numbers and solder ball size will increase additional assembly costs. In recent years, the industry has developed Fan-out WLP can solve the above traditional WLP integration challenges. For Infineon in 2006 proposed the Fan-out WLP Technology [1-3]. In the Fan-out WLP integration process, multichip temporary de-bonding is the most important key technology. In recent times, a lot of studies for the de-bonding process to make wafer release, including chemical dissolution, thermal release device and laser ablation technology. There exist a number of approaches to the de-bonding of thinned device wafers: they may be released by exposure to chemical solvents delivered through perforations in the handler, by mechanical peeling from an edge-initiated separation point, or by heating the adhesive to the point where the silicon device wafer may be removed by sheering or peeling [4]. The de-bonding process for Fan-out WLP needs low-temperature and zero-force de-bonding. Therefore, this paper used the UV laser ablation de-bonding technology which process can use a glass substrate and can be handled at low temperature. The UV laser de-bonding process has been successfully achieved to apply in Fan-out WLP.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122811291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Novel impedance matching technique for pogo pin design","authors":"Chee-Hoe Lin","doi":"10.1109/EPTC.2016.7861535","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861535","url":null,"abstract":"Physical parameters of a pogo pin that can influence the pogo pin characteristic impedance are identified. A coupled impedance extraction method is used to extract the characteristic impedance of a pogo pin. An impedance matching technique is introduced, utilizing commercial software. A pin design experiment is presented, parameterizing the pogo pin geometry, optimizing the characteristic impedance to meet the S-Parameter requirements.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122489200","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Bromine induces corrosion in reliability test","authors":"N. H. Lee, Cheng-Fu Yu, O. O'Halloran, A. Firiti, Z. Acar, N. Cannesan, Y. W. Hao, Jyun Ji Chen, Johan Tsai, Peter Sun, Sharon Chen","doi":"10.1109/EPTC.2016.7861537","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861537","url":null,"abstract":"The Ball grid array (BGA) product fixed on the PCB under Highly Accelerated Stress Test (HAST) reliability test and its relevant corrosion phenomenon are reported. In this article, BGA performed HAST with the socket which individually interconnect between BGA device and PCB test board is subjected to provide moisture path and transfer the applied bias to the PCB. Oxidation and corrosion are found on the SnAgCu solder balls. Moreover, Br contained byproduct on some specific solder ball surface is observed, too. Those phenomenon is examined by 3D microscope, high kV Energy dispersive spectrometer (EDS) and Xray photoelectron spectroscopy (XPS). The Br ion source mainly migrates from PCB solder mask to solder balls, so the PCB without solder mask does not present corrosion and the corresponding Br byproduct. It is also found that different electrical bias/current configurations applied on the solder balls will impact the solder ball corrosion and by product formation. It is suggested that electron chemical migration take place in this case.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114397107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Modeling of differential vertical transition with through silicon vias (TSVs) in 3D die stack","authors":"K. Chang","doi":"10.1109/EPTC.2016.7861444","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861444","url":null,"abstract":"In this paper, a differential vertical transition with through silicon vias (TSVs) in photonic integrated circuit die is presented. The vertical transition composes of TSVs providing connectivity between the die front side and back side, BEOLs and micro-bumps. No back side redistribution layer is required to keep the fabrication process simple with good electrical performance. The high frequency characteristic of the differential TSV structure is also studied to provide design guidelines for the differential vertical transition. The effects of TSV pitch, liner oxide thickness and TSV mismatch on the high frequency performance are demonstrated. The change in TSV pitch has impact on the differential mode insertion loss and differential mode impedance matching while the liner oxide thickness variation induces negligible effect. Moreover, the TSV mismatch on the differential to common mode conversion is also not critical. The proposed differential transition design acquires simulated differential mode insertion loss of better than 0.75 dB up to 50GHz and simulated differential mode return loss of greater than 14 dB from DC to 50 GHz.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117320310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Development of UHF to 2.4GHz and 5.2GHz dual band up-conversion CMOS mixer","authors":"Ryoya Miyamoto, A. Galal, H. Kanaya","doi":"10.1109/EPTC.2016.7861471","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861471","url":null,"abstract":"This paper presents the development of an up conversion mixer for wireless transmitter application in a 0.18-μm CMOS technology. The designed up-conversion mixer input center frequency is 620MHz and the output is 2.4GHz and 5.2GHz, respectively, for white space of TV broadcast frequency (470∼710MHz) communication system. In this design, it is become available by constructing dual band filter using bonding wires and chip inductors. The mixer is designed using TSMC 0.18μm CMOS process. Circuit simulations and measurements had been performed. The proposed mixer has a simulated conversion gain of 15.5dB and 16.2dB, IIP3 of −3.35dBm and −1.76dBm, noise figure of 5.32dB and 5.32dB at 2.4GHz and 5.2GHz.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128383423","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}