2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)最新文献

{"title":"Analysis of crack and dislocation of direct wafer bonded silicon diaphragm","authors":"L. E. Khoong, T. K. Gan","doi":"10.1109/EPTC.2016.7861487","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861487","url":null,"abstract":"Crack and dislocation of direct wafer bonded silicon diaphragm on silicon dioxide layer of silicon substrate containing cavity were analyzed. Scanning electron microscopy (SEM), energy dispersive X-ray spectroscopy (EDX) and focused ion beam (FIB) were conducted on cracked silicon diaphragm to understand the mechanisms of crack initiation and propagation. SEM analysis results show that the crack initiated at the bottom of the silicon diaphragm and subsequently propagated toward to the top surface of the silicon diaphragm. Further FIB (focused ion beam) and TEM (transmission electron microscope) analyses show the presence of dislocations at silicon diaphragm and the bonding interface (i.e. silicon/silicon dioxide interface). Crack initiation and propagation mechanisms were discussed based on the SEM, FIB/SEM, EDX and TEM analysis results.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"22 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120913637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Optimization of electronic enclosure design for thermal and moisture management using calibrated models of progressive complexity","authors":"S. Mohanty, Z. Staliulionis, P. S. Nasirabadi, R. Ambat, J. Hattel","doi":"10.1109/EPTC.2016.7861525","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861525","url":null,"abstract":"The thermal and moisture management of electronic enclosures are fields of high interest in recent years. It is now generally accepted that the protection of electronic devices is dependent on avoiding critical levels of relative humidity (typically 60–90%) during operations. Leveraging the development of rigorous calibrated CFD models as well as simple predictive numerical tools, the current paper tackles the optimization of critical features of a typical two-chamber electronic enclosure. The progressive optimization strategy begins the design parameter selection by initially using simpler equivalent RC-circuit models for concentration of water vapor and temperature in the electronic enclosure. After reducing the potential parameter-value space for the critical features using the RC-approach, the optimization strategy uses simpler 2D CFD models of temperature and moisture transport to further focus the parameter-value space, before shifting to 3D CFD models for final evaluations and verification. The approach results in a system capable of predicting optimum design features for the thermal and moisture management of electronic enclosures in a time-efficient and practically implementable manner.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114701993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High bandwidth interconnect design opportunities in 2.5D Through-Silicon interposer (TSI)","authors":"R. Weerasekera, K. Chang, Songbai Zhang, G. Katti, Hong Yu Li, R. Dutta, J. R. Cubillo","doi":"10.1109/EPTC.2016.7861479","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861479","url":null,"abstract":"Silicon interposer technology enables the integration of multiple silicon dies on it providing fine pitch interconnects for die-to-die communication and Through-Silicon Vias (TSVs) for package/PCB level connections. Therefore, this technology has been identified as a viable solution for logic and memory types of applications where higher bandwidth in required. In the paper, we characterize thick (t=3μm; w/s=3μm/3μm) as well as thin (t=1μm; w/s=2μm/2μm) front side die-to-die Cu interconnects along with chip-to-substrate interconnects containing Through-Silicon Vias (TSVs) and estimate the data transfer capabilities of them. Evaluation of digital signal interconnect performance shows that the maximum bandwidth requirements expected by the latest memory technologies can be achieved by the silicon interposer technologies characterised in this paper.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127902670","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Test method to evaluate a robust ball grid array (BGA) ball mount flux","authors":"Sheng-Hung Chou, Yan Liu, M. Durham, S. Lim, T. Fang, Y. Hsiao","doi":"10.1109/EPTC.2016.7861555","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861555","url":null,"abstract":"A ball grid array (BGA) is a type of surface-mount package used for integrated circuits. In more advanced technologies, solder balls may be used on both the PCB and the package. Also, in stacked multi-chip modules, solder balls are used to connect two packages. The process steps prior to the final BGA ball mount process are becoming increasingly complex, which will induce BGA pad surface oxidation and contamination. Both the surface oxidation and contamination can result in the missing ball or ball bridge defect which causes major yield loss during ball mounting. Another alternative is to use organic solderability preservatives (OSP) to protect the pad surface from oxidation. However, the OSP substrate ball mount process necessitates an additional flux pre-clean step to remove the OSP prior to normal ball mount process. In this work, a novel BGA ball mount flux has been developed and different test methods were used to verify its stability and wide-range application. The study uses five different test methods, including a wetting test under different preconditioned (none/baked/bake and cleaned/double-baked and cleaned) coupons to simulate real product conditions. The Movement During Reflow (MDR) test is used to simulate flux outgassing and other effects on BGA ball movement during reflow. Secondary Ion Mass Spectrometry (SIMS) is used to study the flux clean capability on pre-process oxidation / contamination of NiAu and OSP pad finishes.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131971674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Friction wear test evaluation for assembly tool","authors":"O. Ho, A. Yeo, T. H. Guan, Ng Lay Peng, C. Wai, Lum Chee Choong","doi":"10.1109/EPTC.2016.7861489","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861489","url":null,"abstract":"Conventional method to define the useful tool life is by punching the actual molded units in trim and form (TNF) machine. Throughout the punch intervals, the punched leadframes were sent for inspection for any side burr observed at the leads. This process might take several days or weeks in order to reach the end of punch tool lifespan. It is quite a manual and time consuming task, if it involves several types of punch tool to be examined. Beside that, this method does not capture the wear rate of the punch tool. This paper demonstrates the friction wear test of punch tool to obtain the wear rate using Bruker Tribolab UMT tester, which is equipped with reciprocating drive. The punch tool is hold stationary at the carriage (z axis), and rub against the dummy molded unit, which oscillated by the reciprocating drive. The volume loss of the punch tool is plotted against the number of reciprocating cycles to determine the wear rate. The wear mode of the punch tool is investigated at end of the test. From the results of this study, it is shown that the punch tool's volume wear vs the reciprocating cycles fit well with the linear line. The wear rate of punch tool is calculated from the slope of the linear line.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131544053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fine pitch RDL patterning characterization","authors":"Chen Bing, Soh Siew Boon, H. Wee, Jung-Bo Yang","doi":"10.1109/EPTC.2016.7861566","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861566","url":null,"abstract":"Lithography is a key enabling technology for semiconductor devices and circuits. The CMOS scaling continues to drive lithography to sub-10 nanometers resolution. The challenges of advanced wafer level packaging (WLP) are very different from CMOS technology. Generally, advanced WLP process requires not only good critical dimension control and nearly 90 degree vertical resist profile, but also requires scum free after photoresist development, good resist adhesion during electroplating and residual free resist stripping performance. In this paper we studied a new Redistribution layers (RDL) process based on 2um thickness chemical amplified resist (CAR) to resolve 1um post lithography critical dimension (CD) design. The performance comparison between our existing in house 2um thickness naphthoquinonediazide (NQD) and CAR photoresist were based on critical dimension uniformity (CDU) and Copper (Cu) electroplating performance. The final results were promising for printing RDL at 1um critical dimension (CD) and thickness with integrated solution for advanced WLP.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130963384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Reliability evaluation of copper (Cu) through-silicon via (TSV) barrier and dielectric liner by electrical characterization","authors":"J. Chan, Xu Cheng, K. Lee, W. Kanert, C. S. Tan","doi":"10.1109/EPTC.2016.7861524","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861524","url":null,"abstract":"The purpose of this study is to analyze the failure mechanisms of copper (Cu) through silicon via (TSV) with titanium (Ti) barrier and silicon dioxide (SiO2) dielectric liner, following various stress tests such as electrical, temperature cycling (TC) and high temperature storage (HTS) via electrical characterization methods. The various stresses are performed individually or in a combination of TC or HTS with electrical bias for comparison. Capacitance-voltage (C-V) and current density-electric field (J-E) characteristics were plotted after the respective stresses, to detect any changes in its electrical characteristics. Results from C-V and J-E plots suggest that barrier degradation is related to material and structural influence. The degradation in the barrier layer can lead to Cu diffusion and drift into the dielectric layer, which is reflected by changes to the minimum depletion capacitance measured in the C-V curve. An increase or decrease in the minimum depletion capacitance measured indicates Cu ions presence in SiO2 or silicon (Si) substrate respectively. The individual stresses performed reveal that there was insignificant copper existence in the dielectric layer. However a combination of stresses which involves an additional electrical bias stress on TC or HTS sample better enabled the detection of degraded barrier by electrical means. The electrical bias serves as a driving force for Cu ions drift through degraded barrier as Cu does not readily diffuse into SiO2 at room temperature. On the other hand, by increasing the number of TSVs measured in an array structure, it is found that degraded barrier and Cu trace was detected without the need for subsequent electrical bias stress.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133398917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Multi-port high bandwidth interconnect equivalent circuit model for 3.2 Gbps channel simulation","authors":"Hui Lee Teng, Yee Huan Yew","doi":"10.1109/EPTC.2016.7861558","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861558","url":null,"abstract":"S-parameter is commonly used for channel modeling and crosstalk modeling between channels in high speed digital design. However, for I/O buffer circuit designer, S-parameter models are not well received owing to all general frequency domain data is difficult to incorporate into a transient circuit simulation. S-parameter is a frequency domain data and is difficult to deal in a transient circuit simulation especially when S-parameter is broadband with multi-port as well as causality and passivity issues exist. Hence, Spice model or Spice-equivalent model is needed for transient circuit simulation. A lumped-elements Spice model only allows circuit designers to perform accurate simulation at lower data rate. In high speed design, lumped-elements Spice model does not provide sufficient bandwidth for accurate transient simulation analysis. Therefore, there is a need to create high bandwidth Spice model with sufficient bandwidth to support accurate channel transient circuit simulation. This paper discusses the creation of high channel count package equivalent circuit models for channel timing analysis in 3.2Gbps range. It highlights the challenges in developing the methodology to accurately deliver a high channel count and high bandwidth Spice-equivalent sub-circuit models which is compatible with Spice-based circuit simulator. The modeling methodology improves simulation run time and preserving passivity as well as the causality of the compact circuit model while maintaining the original S-parameter behavioral model. The proposed high bandwidth model offers dramatically faster simulation time without sacrificing accuracy. The resultant of this study will allow more aggressive and accurate signal integrity analysis.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"SE-13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127236759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Integration of MEMS/Sensors in Fan-Out wafer-level packaging technology based system-in-package (WLSiP)","authors":"A. Cardoso, S. Kroehnert, R. Pinto, Elisabete Fernandes, Isabel Barros","doi":"10.1109/EPTC.2016.7861591","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861591","url":null,"abstract":"The Internet of Things/ Everything (IoT/E) will require billions of single or multiple MEMS/ Sensors integrated in modules together with other functional building blocks like processor, memory, connectivity, built-in security, power management, energy harvesting, and battery charging. The success of IoT/E will also depend on the selection of the right Packaging Technology. The winner will be the one achieving the following key targets: best electrical and thermal system performance, miniaturization by dense system integration, effective MEMS/ Sensors fusion into the systems, manufacturability in high volume at low cost. MEMS/ Sensors packaging in low cost molded packages on large manufacturing formats has always been a challenge, whether because of the parameter drift of the sensors caused by the packaging itself or, as in many cases, the molded packaging technology is not compatible to the way MEMS/Sensors are working. Wafer-Level Packaging (WLP), namely Fan-Out WLP (FOWLP) technologies such as eWLB, WLFO, RCP, M-Series and InFO are showing good potential to meet those requirements and offer the envisioned system solutions. FOWLP will grow with CAGR between 50–80% until 2020, forecasted by the leading market research companies in this field. System integration solutions (WLSiP and WL3D) will dominate FOWLP volumes in the future compared to current single die FOWLP packages for mobile communication. The base technology is available and has proven maturity in high volume production, but for dense system integration of MEMS/ Sensors, additional advanced building blocks need to be developed and qualified to extend the technology platform. The status and most recent developments on NANIUM's WLFO technology, which is based on Infineon's/ Intel's eWLB technology, aiming to overcome the current limits for MEMS/ Sensors integration, will be presented in this paper. This will cover the processing of Keep-Out Zones (KOZ) for MEMS/ Sensors access to environment in molded wafer-level packages, mold stress relief on dies for MEMS/ Sensors die decoupling from internal package stress, thin-film shielding using PVD seed layer as functional layer, and heterogeneous dielectrics stacking, in which different dielectric materials fulfill different functions in the package, including the ability to integrate Microfluidic.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114333447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Integration of low temperature PECVD deposited silicon oxides with advanced packaging","authors":"Chunmei Wang, Steven Lee, Xiangy-Yu Wang, K. Chui, Mingbin Yu","doi":"10.1109/EPTC.2016.7861542","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861542","url":null,"abstract":"In this study, low temperature TEOS oxides were deposited by plasma enhanced chemical vapor deposition (PECVD) at 100°C, 150°C and 180°C respectively. After deposition, physical characterization was carried out by FTIR for chemical bonding condition, AFM for surface roughness, Auger electron spectroscopy for chemical composition, ellipsometer for refractive index, and DHF for wet etching rate measurement. All characterization data shows that the TEOS oxide deposited at 100°C is comparable with the higher temperature deposited TEOS oxide. Integration with TSV technology to act either as liner dielectrics for Cu Via was performed as well to confirm the feasibility of these low temperature deposited TEOS oxide to be integrated in TSV technology in terms of process. E-test for blind TSV leakage and capacitance was also carried out and compared. The e-test data indicates that TEOS oxide deposited at 100°C has exhibited comparable electrical performance as 150°C and 180°C deposited TEOS oxide.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114583823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}