2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)最新文献

{"title":"Study of de-gate remnant resolution with high reliability performance moulding compound","authors":"S. Ng, H. T. Wang, F. Goo","doi":"10.1109/EPTC.2016.7861532","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861532","url":null,"abstract":"Ever increasing stringent reliability requirements in semiconductor package demands a mold compound with a property of resisting package crack under stress condition of High Temperature Storage (HTS) at 175°C, compatible with package assembly material such as copper interconnect, High Humidity High Temperature Gate Stress (H3TGS) as well as meeting second level reliability test in Thermal Cycle on Board (TCoB). Such property would require a molding compound that has higher adhesion, higher cross link density and storage modulus in order to provide good protection over the chip and interconnect. These properties, however, would mean a higher adhesion molding compound that results in a harder-to-degate mold area, leaving mold remnant on the lead-frame runner after molding operation and leads to assembly yield loses. Material analysis, extended reliability test, design revision on mold de-gating tool and leadframe, molding parameter optimization are conducted in order to minimize molding runner remnant and subsequently improve molding assembly yield. Extended reliability test of H3TGS at 175°C, HTS 175°C and 6000 cycle of TCoB has been performed with package A to identify the right formulation selection for mold compound and impurities level. Several iterations to the DOE are done throughout the studies. Brainstorming session produced a list of molding parameters and mechanism potentially leading to the mold remnant. Using the button shear test at various temperature, adhesion of various mold compounds at various temperature and contact area are identified to have greatest impact. A design of experiements focusing on cooling station design & cooling time are performed. Additionally, contact area of mold compound to leadframe are also being considered to reduce the remnants rate. It reveals that mold remnant occurrence on package A has failure rate of 60%. By using the selected high performance mold compound on package B, the result is much better with almost no mold remnant observed on the runner area due to much lesser contact. Therefore a correlation of contact area versus remnant rate has been established, and package A leadframe is being redesigned together with the de-gating tool and thus this improve the remnant to 1%.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128391921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Investigations on the oxide removal mechanism during ultrasonic wedge-wedge bonding process","authors":"Y. Long, F. Dencker, F. Schneider, B. Emde, Chun Li, J. Hermsdorf, M. Wurz, J. Twiefel","doi":"10.1109/EPTC.2016.7861512","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861512","url":null,"abstract":"As an inevitable step during ultrasonic bonding of aluminum or copper materials, the removal of oxides that prevent the bond formation is essential for obtaining high quality. Nevertheless, the oxides removal process is still unclear after tens of years' application of ultrasonic bonding. In this project, the removal mechanism was investigated via the analysis of an artificially coated oxide layer. The oxide removal process was observed in real-time by a high-speed observation system and the oxides distribution after the bonding process was observed under an electron microscope. The results show that during the bonding process, the detached oxides first agglomerate into larger particles and were then pressed outside of the contact area. The areas of the particles were counted and fit to a lognormal distribution.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127189870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Extremely low warpage coreless substrate for SiP module","authors":"Tang-Yuan Chen, Meng-Kai Shin","doi":"10.1109/EPTC.2016.7861449","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861449","url":null,"abstract":"The system-in-Package (SiP) module market has grown significantly over the past several years and it is now one of the fastest growing packaging technologies in the semiconductor industry driven by lower cost, smaller form factor, higher levels of integration and better performance. In addition, for handheld and mobile application the coreless substrate had been evaluated to replace buildup coded substrate not only thinner thickness but superior electrical performance. However, coreless substrate causes severe package warpage issue due to lack of rigid and low CTE core. In this work, the three Dimensional (3-D) aMA, as a non-contact optical deformation measurement method were carrier to explore and compare strip substrate warpage performance between cored and coreless substrate. To reduce the warpage issue of coreless substrate, the parametric factors on the structure and material would be investigated. These design guides are then studied by finite element modeling to understand mechanism for warpage improvement. From the result, it shows that the strip substrate warpage of coreless is higher 4∼5 times than cored substrate. Besides, the dielectric material property selection is critically factor for warpage control. Furthermore, asymmetric thickness design of cu layer and soldermask layer is another effective for warpage reduction. The bottom layers of Cu and soldermask should be thicker than top layers. A structural design and material property selection guides is then proposed.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131849703","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thin copper wire under extreme HTSL stress duration: Crack failure mechanism characterization","authors":"R. E. Vaion, A. Mancaleoni, L. Cola, M. De Tornasi, P. Zabberoni","doi":"10.1109/EPTC.2016.7861522","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861522","url":null,"abstract":"Mission profiles for specific automotive applications are becoming more and more demanding from the reliability point of view. Translating this challenging requirements into reliability targets, it means performing trials for longer duration, or using more accelerated conditions (increasing temperature or voltage, etc…). This study is focused on the understanding of the failure mechanism and the characterization of a thin copper wire over Aluminum pad submitted to a very long stress duration at high temperature: more than 5000hrs @150°C. Going beyond AEC-Q100 Grade 1 (1000hrs @150°C) [1] and AEC-Q006 (2000hrs @150°C) [2] specified conditions for copper wires, it has been possible to observe the effects of the isothermal stress experienced by the Cu/Al bonding system, up to its wear out. Such critical conditions often activate failure mechanisms not significantly observable in standard qualifications. After thousand hours at high temperature a crack between Cu ball and CuxAlx IMC (Inter-Metallic Compounds) propagates from the ball edge to the ball center, affecting all the bonding area and causing an open contact. Crack propagation has been evaluated as second order effect of IMC growth and evolution, so its appearing is predictable by the Arrhenius law. The activation energy for the failure rate prediction has been estimated from the experimental data.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130759109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Process considerations, process challenges and manufacturing systems for roll-to-roll processing","authors":"X. Shan, S. Chen, B. Salam, M. B. Mohahidin, J. Wei","doi":"10.1109/EPTC.2016.7861568","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861568","url":null,"abstract":"In roll-to-roll processing, the feeding speed of substrate ranging from several meters to several tens meters per minutes are required for some processes, such as roll-to-roll coating or gravure printing; reducing the speed will lead to other problems. On the other hand, some other processes need prolonged dwelling or holding time, such as thermal embossing. In the case of integrating different processes (for example, embossing and printing) into one roll-to-roll processing line, it is necessary to synchronize the feeding speeds of different processes. In this study, we will focus on thermal embossing process, discuss how the process speed, holding time will affect the fidelity of formed structures. Based on our investigation and comparison, we identified the problems of roll-to-roll thermal embossing, and developed a novel roll-to-roll embossing system. The developed system consists of two metallic belts — the top belt used for embossing template and the bottom belt for carrier. The developed system allows active driving from both sides of polymer films; it also provides an extended template-film contact time even with high speed roll-to-roll thermal embossing. This allows the roll-to-roll embossing to be integrated with other roll-to-roll manufacturing processes such as printing or coating.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131022712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A study on optimization of process parameters, microstructure evolution and fracture behavior for full Cu3Sn solder joints in electronic packaging","authors":"P. Yao, Xiaoyan Li, X. Liang, Bo Yu","doi":"10.1109/EPTC.2016.7861459","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861459","url":null,"abstract":"For understanding full IMCs solder joints comprehensively, the widely used Cu-Sn system was adopted as the research object. A study on optimization of process parameters, microstructure evolution and fracture behavior for full Cu<inf>3</inf>Sn solder joints in electronic packaging was conducted systematically. For forming full Cu<inf>3</inf>Sn solder joints, 260°C, 1N, 5h was determined as the optimal parameter combination. At 260°C and 1N, planar Cu<inf>6</inf>Sn<inf>5</inf> was first precipitated at Cu-Sn interface, which was followed by the formation of planar Cu<inf>3</inf>Sn. Until the total consumption of residual Sn, the Cu<inf>6</inf>Sn<inf>5</inf> continued to grow with a transition from the planar shape to scallop-like shape, while the Cu<inf>3</inf>Sn continued to grow with a round-trip change from the planar shape to wave-like shape. After the formation of full IMCs solder joints including Cu<inf>3</inf>Sn and Cu<inf>6</inf>Sn<inf>5</inf>, the Cu<inf>3</inf>Sn continued to grow at the expense of Cu<inf>6</inf>Sn<inf>5</inf> until full Cu<inf>3</inf>Sn solder joints were obtained by 300min. When the loading rate was 0.001mm/s, 0.01mm/s and 0.1mm/s respectively, the shear strength of full Cu<inf>3</inf>Sn solder joints was 46.1MPa, 50MPa and 60.5MPa correspondingly. Through analysis of fracture surface, we found that different microscopic fracture mechanisms led to different strength of full Cu<inf>3</inf>Sn solder joints when the loading rate was varied.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115111206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Study of dielectric materials coating conformality and adhesiveness on epoxy mold compound surface","authors":"B. L. Lau, D. Ho, H. Hsiao, K. Yamamoto","doi":"10.1109/EPTC.2016.7861435","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861435","url":null,"abstract":"Dielectric material coating process on the surface of epoxy mold compound has been successfully developed for fan-out wafer level packaging. This paper introduces the pretreatment process and conditions required for dielectric coating, coating process and the studies of dielectric material coating conformality and adhesiveness on epoxy mold compound, silicon and copper surface. The DOE of these film deposition process parameters was performed to develop the pretreatment process conditions for dielectric. Coating conformality was studied here to decide the optimized conditions. 250μm solder bump reflowed on UBM is the test structure to examine the strength of the dielectric adhesion on the silicon and epoxy mold compound surfaces through shear test. This shear test results is compared with the similar test structure which the dielectric material was coated on the copper surface built-on silicon substrate. Failure mode analysis using microscope is carried out to evaluate the bonding strength of individual layers. A further evaluation on the reliability of solder joint, dielectric adhesiveness and failure mode will be performed. [1], [2]","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114067952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Highly efficient and flexible plasma based copper coating process for the manufacture of direct metallized mechatronic devices","authors":"M. Mueller, J. Franke","doi":"10.1109/EPTC.2016.7861506","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861506","url":null,"abstract":"The plasma based copper coating process is an innovative process for the production of planar or three dimensional circuit carriers. Both conductor lines for logic circuits and conductors for high power transmissions can be realized. This paper describes the manufacturing process chain of direct metallization by plasma based copper coating and shows the potentials of this technology. Circuits can be applied to almost any base substrate such as polymers, ceramics or even metal since an insulating dielectric lacquer layer separates the substrate from the metallization. In contrast to previous plasma based copper depositing processes the digital direct metallization enables clearly defined fine structures without using any inflexible and high-maintenance masks [1]. An enormous advantage of this procedure is the complete elimination of wet chemical process steps, which are known from the laser direct structuring method (LDS) [2]. In addition to diverse characterizations this paper represents the opportunities of the technology by means of demonstrator applications.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121093519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Embedding of wearable electronics into smart sensor insole","authors":"M. Hubl, O. Pohl, V. Noack, P. Hahlweg, C. Ehm, M. Derleh, T. Weiland, E. Schick, Hugo Müller, D. Hampicke, P. Gregorius, T. Schwartzinger, T. Jablonski, J. Maurer, R. Hahn, O. Ehrmann, K. Lang, E. Shin, H. Ngo","doi":"10.1109/EPTC.2016.7861550","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861550","url":null,"abstract":"The number of elderly and care dependent persons is continuously increasing. The percentage of people over 60 years rises worldwide from 10% in 2000 to 21 % of the world's population in 2050. [1] The usage of wearable sensors in combination with telemedicine have a big potential to ensure a continuous healthcare and nursing of chronically ill and old patients and to enable them an independent life into old age. [2] The development and assembly of a modular low-power multi-sensor platform with wireless data transmission allows to set up a specific sensor network depending on location and application on the body. The wearable electronics consisting of a gyroscope, temperature and pressure sensors and low-power microcontroller with Bluetooth transmitter are integrated into a shoe insole and encapsulated in silicone as a first prototype. This smart sensor insole measures the vital and body data to monitor the patient's physical activity. Advanced sensor analysis enables to detect a fall of the wearer, which can be triggered to call for help from nurses or relatives. In a further development an energy harvesting version including a rechargeable microbattery and battery management system leads the way to an energy-autarkic operation and maintenance-free telemedical patients monitoring for homecare and ambient assisted living of our aging and digitalized society.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124692374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Performance modeling and broadband characterization of chip-to-chip interconnects with rough surfaces","authors":"Somesh Kumar, Rohit Sharma","doi":"10.1109/EPTC.2016.7861556","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861556","url":null,"abstract":"Planar copper interconnects suffer from surface roughness that results in their performance degradation. In this paper, we investigate the role of rough conductor surfaces on the electrical performance of chip-to-chip interconnects using 3D full wave simulation. Various interconnect performance metrics, such as delay, energy-delay product, bandwidth density, insertion loss and signal attenuation are evaluated over broadband frequencies. Our results show that rough conductor surfaces can significantly influence these metrics. In that, the maximum penalty on insertion loss, attenuation, delay, energy-delay product and bandwidth density is 50%, 86%, 3X, 3.7X and 28%, respectively. Finally, we report the computational overhead for simulating high-speed interconnects with rough surfaces.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127369404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}