2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)最新文献

{"title":"Thermal design and analysis of high power SiC module with low profile and enhanced thermal performance","authors":"Tang Gongyue, Lee Jong Bum, C. T. Chong","doi":"10.1109/EPTC.2016.7861595","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861595","url":null,"abstract":"In this study, a silicon carbide (SiC) device based power module with low profile and enhanced thermal performance is explored. The low profile is achieved by embedded the SiC chips into the direct bonded copper (DBC) substrate which is designed with cavities. The enhanced thermal performance is achieved by eliminating the core layer of the DBC substrate and shortening the thermal path from the SiC Chip (heat source) to the cold plate (heat sink). Furthermore, a flat surface on the top side of the power module is achieved by designing and positioning the top copper clips in the same level as the top copper trace of the DBC substrate. As such a second liquid cooled cold plate can be implemented on the top surface of the module to further enhance the thermal performance of the power module through the dual side liquid cooling solution. The simulation results show that the chip junction to case thermal resistance for the proposed power module is about 50∼60% of the chip junction to case thermal resistance for the conventional power module with similar size and power rates. By applying double side liquid cooling to the proposed power module which is not adaptable for the conventional power module, the thermal performance of the proposed power module further increased about 20%.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121837681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Stabilization and utilization of coupling MOS capacitance between TSVs","authors":"R. Fang, Huan Liu, M. Miao, Xin Sun, Yufeng Jin","doi":"10.1109/EPTC.2016.7861502","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861502","url":null,"abstract":"Through-silicon via (TSV) is a key enabler for future 3-D integrated circuits. Due to MOS (Metal-Oxide-Semiconductor) effect, the coupling capacitor between TSVs is actually a varactor under different signal/power voltages. This paper offers a discussion on the stabilization and utilization of the TSV varactor for different systems. For digital systems, it is important to ensure that TSV capacitance is stable within the operating voltage. Therefore, different methods are proposed and compared to stabilize the TSV coupling capacitance. For reconfigurable systems, the possibility of the TSV varactor serving as the tunable capacitor is demonstrated by designing a voltage-controlled tunable low-pass filter with a TSV pair. The doping profile of the substrate is modified to maintain a reasonable quality factor of the TSV varactor. The simulated results show that the filter has a cutoff frequency shifting from 1.85GHz at OV to 2.23GHz at 1V, resulting in a tuning range of ±9% centered at 2.04GHz.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122067702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Reliability study of No Clean chemistries for lead free solder paste in vapour phase reflow","authors":"Emmanuelle Guéné, Aurélie Ducoulombier","doi":"10.1109/EPTC.2016.7861463","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861463","url":null,"abstract":"Some limitations are observed on complex high density boards with convection ovens processing lead free alloys. Vapour phase soldering process offers excellent heat transfer capabilities and high wetting performance, and it has become a real option to be considered, including medium to high volume production, in high reliability applications. Traditionally, pastes used in such process were designed to be cleaned after reflow as they were mainly dedicated to aeronautics or military. Today, other electronics assembly markets (industry, automotive) are looking for No Clean pastes able to stand both convection and vapour phase reflow. Peak temperatures are much lower in a vapour phase oven: flux activators may not be fully consumed because oxidation is minimized. Flux residues remaining on the boards may cause corrosion in harsh environment, even when using no-clean solder pastes. Firstly, the cleanability of several no-clean solder pastes will be compared after vapour phase and after convection soldering. Different defluxing processes are considered. Secondly, the chemical reliability of the same group of No Clean pastes will be assessed after vapour phase reflow in comparison to convection reflow. Surface insulation resistance (SIR) and electrochemical migration (ECM) will be used as a first tool. Then Bono corrosion test will be used. The behaviour of several No Clean solder pastes, in terms of cleanability and chemical reliability will be described according to the reflow process applied.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"52 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116619623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"How to feed enough to greedy IoT monster","authors":"K. Otsuka","doi":"10.1109/EPTC.2016.7887893","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7887893","url":null,"abstract":"IoT changes greedy monster now-a-day. That seems to be uncontrollable world. Mega-data centers (DC’s) are trying to catch the monster mainly in the US. These systems included even edge center ones are in blind as like fog weather because the DC’s providers have been developed by own inside technologies. In our historically seen, the concept has been undergoing as “high-end technologies automatically shift to low-end ones”. So we want to know what the blind out. In my experiences, some of specific examples show by that could reveal the blinds and get the evidence. The most important element on their thought is communication bandwidth that is directly affected the data processing performance and communicating each other. The way for getting wider bandwidth involves three approaches which are high speed clocking, many lanes and high data compression. The first two issues relate with packaging technology which would be presented some. We additionally consider data compression technology. The system performance balance should put together the three issues. Let’s focus in the three issues now. While power saving is another one of the most important things in not only DC’s but mobiles. Higher bandwidth introduces saving power that we should know. Architecture of data processing with low power is managed by packaging issues which focus in also. If you well done of it, the world's highest-volume IoT platforms, the largest commercial health data clouds, the largest commercial video platforms and so on even in mobile fields could be taken as far as technological basis.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116962113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Investigation on the influence of phosphor particle size gradient on the optical performance of white light-emitting diodes","authors":"Jiaqi Wang, S. Lee, Huayong Zou","doi":"10.1109/EPTC.2016.7861483","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861483","url":null,"abstract":"In this study, the influence of phosphor particle size gradient on the optical performance of white light-emitting diodes (WLEDs) was investigated. Three multi-size phosphor layer structures with different size gradients were proposed. The YAG:Ce phosphor particles of 3 μm and 13 μm were configured at three different locations to form the size gradient. Both simulation and experimental investigations were performed to characterize the optical performance of WLEDs. In the simulation, the proposed WLED packages were modeled by a ray-tracing algorithm, where optical constants were obtained from the Lorenz-Mie theory. In the experimental investigation, a double dispensing-curing method was employed for the fabrication of dual phosphor layer structures. The radiant power, luminous efficacy, correlated color temperature (CCT) as well as angular color uniformity (ACU) were used as the key criteria to evaluate the optical performance.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115620714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Plasma etching of SiO2 with tapered sidewall for thin film encapsulation","authors":"V. Bliznetsov, Bin Li, Jaewung Lee, Huamao Lin","doi":"10.1109/EPTC.2016.7861569","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861569","url":null,"abstract":"We proposed the way to solve the problem of cracks in AlN cap layer for thin film encapsulation of MEMS. By development of sacrificial SiO2 etching with smooth tapered sidewall, the quality of subsequently deposited AlN cap layer is improved and reliable device sealing is achieved with a single cap layer.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123332532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Leadframe alloys Cu-Fe-P and Cu-Cr as an alternative to Cu-Zr for wheel-speed magnetic sensor package","authors":"Matthew M. Fernandez, Richard Jan C. Malifer, E. A. Gonzales","doi":"10.1109/EPTC.2016.7861465","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861465","url":null,"abstract":"Investigations of alternative Cu-based alloys were carried out as an opportunity for improvement on the quality, reliability and cost reduction. CuFeP and CuCr were successfully evaluated as an alternative leadframe alloys to the existing CuZr alloy on a wheel-speed magnetic sensor package through thermo-mechanical simulation, assembly and test performance, and reliability tests performance. Material properties and themo-mechanical simulation of the leadframe alloys showed that the CuFeP and CuCr alternative alloys have higher resistance to elastic and plastic deformations than the existing CuZr alloy. The assembly, final test, and reliability tests performances of the samples built using CuFeP and CuCr alternative alloys proved that the ferromagnetic impurities did not affect the functionality of wheel-speed magnetic sensor device inside the package. Furthermore, the leadframe-to-mold adhesion performance of the CuFeP and CuCr alternative alloys also showed outstanding result as compared to the existing CuZr alloy.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121050980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Through mold interconnects for fan-out wafer level package","authors":"S. W. Ho, L. Wai, S. A. Sek, Daniel Ismael Cereno, B. L. Lau, H. Hsiao, T. Chai, V. S. Rao","doi":"10.1109/EPTC.2016.7861441","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861441","url":null,"abstract":"Through mold interconnects (TMI) is a key enabler for fan-out wafer level packaging (FOWLP) for 3D integration. Three different types of TMI have been developed for both mold-first and RDL-first fabrication flow. The three types of TMI consist of laser drilled vias, vertical wire-bonds and Cu pillars interconnect. The process flow and fabrication results of each TMI will be presented in this paper.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"338 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116261195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Package with high thermal conductivity of graphite attached onto die surface to solve hot spot issue","authors":"F. Yen, L. Hung, N. Kao, D. Jiang","doi":"10.1109/EPTC.2016.7861437","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861437","url":null,"abstract":"Currently electrical products such as smart phone and tablet, light weight and thin feature of them are definitely required. To achieve several requirements, size of IC package assembled in limiting space become more crucial and development orientated. So, a lot of IC design factory prefer to make more function loop in one single die to provide high efficient performance application for electric products such as cell phone chip module and graphic card GPU …etc. While, IC with multi function loop in one single die inevitably cause different power dissipation distribution onto die surface and it might accompanies hot spot issue on die surface. Thereby hot spot issue affect overheat problem to reduce IC products performance characteristic during frequently working. Therefore, try to balance die surface temperature distribution is very important work for IC with multi function design. We want to investigate a methodical to find out good solution to balance die surface temperature distribution. However, to add a metal heat sink onto package surface is normal and traditional technique to spread out heat from package surface, but this way can't effectually balance die surface temperature directly. In this paper, we study a new method that to attach a thin heat spreader onto die surface during assembly process. This new method can reduce hot spot issue and balance die surface temperature directly. From this study, we select EDHS-PBGA (Exposed Dropin Heat Sink BGA) package assembly with thin heat spreader on die surface and use Flotherm CAE tool to simulate die surface with different heat spreader material thermal performance comparison. The heat spreader materials are silicon, copper plate, aluminum plate and graphite plate. The graphite plate material is with well specific characteristic of high thermal conductivity as 1600∼1900w/mk for horizontal direction and 6∼10w/mk for vertical direction. Package with graphite plate spreader onto die surface will perform conspicuous temperature balance distribution due to graphite plate with high thermal conductivity parameter index than other material in horizontal direction. We expect this graphite attached onto die surface technology can be popularly apply on IC package process to solve hot spot issue of IC with multi function design.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115838912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Dissolution in service of the copper substrate of solder joints","authors":"Wayne Ng, K. Sweatman, T. Akaiwa, T. Nishimura, Michihiro Sato, C. Gourlay, S. Belyakov","doi":"10.1109/EPTC.2016.7861510","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861510","url":null,"abstract":"It is well known that during service the layer of Cu6Sn5 intermetallic at the interface between the solder and a Cu substrate grows but the usual concern has been that if this layer gets too thick it will be the brittleness of this intermetallic that will compromise the reliability of the joint, particularly in impact loading. There is another level of concern when the Cu-rich Cu3Sn phase starts to develop at the Cu6Sn5/Cu interface and an imbalance in the diffusion of atomic species, Sn and Cu, across that interface results in the formation at the Cu3Sn/Cu interface of Kirkendall voids, which can also compromise reliability in impact loading. However, when, as is the case in some microelectronics, the copper substrate is thin in relation to the volume of solder in the joint an overriding concern is that all of the Cu will be consumed by reaction with Sn to form these intermetallics. This paper reports an investigation into the kinetics of the growth of the interfacial intermetallic, and the consequent reduction in the thickness of the Cu substrate in solder joints made with three alloys, Sn-3.0Ag-0.5Cu, Sn-0.7Cu-0.05Ni and Sn-1.5Bi-0.7Cu-0.05Ni. A simple model developed for the reduction of the Cu thickness as a result of diffusion controlled reaction with Sn to form Cu6Sn5 was found to fit the experimental data well. The results reported in this paper provide an example of the way in which microstructural features that can affect joint reliability are affected by small alloying additions.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128087354","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}