2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)最新文献

{"title":"Wire bond scalable design methodology","authors":"Fee Wah Chong, Yee Huan Yew","doi":"10.1109/EPTC.2016.7861450","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861450","url":null,"abstract":"From the aspect of package design, when ASIC and FPGA are compared, the considerations are vastly different. FPGA design cycle is short and crucial time to market to supports multiple application domains and the package matrix needs to have vertical and horizontal migration. Hence, FPGA package designs need to have scalable design concept to drive short design cycle time for comparatively fast market turn-around time. Scalable design concept is a “Lego” brick approach whereby the module design could be leverage across vertical and horizontal migration of the package matrix. Besides improving the design efficiency, it'll also drive consistent performance across migration packages. To meet cost and resource effectiveness in low cost package, a new scalable design methodology is developed and established. This paper presents the scalable design methodology in wire bond package which involved a new design methodology and process flow in die pad assignment, wire bonding, bond finger placement and ball assignment. The challenges in die-package co-development requirements for the wire bond scalable design concept implementation will be discussed. The advantages and disadvantages of proposed design methodology comparing to conventional design approach from the aspect of design and performance will be studied. In summary, a more efficient scalable design methodology for at least 40% design efficiency improvement was proposed. This new methodology will help to increase the throughput to meet the short time to market for the FPGA package solutions.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124018806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Integrated clean for TSV: Comparison between dry process and wet processes and their electrical qualification","authors":"S. Suhard, Y. Li, A. Iwasaki, S. Van Huylenbroeck, S. Draper, A. Mizutani, T. Dory, F. Holsteyns","doi":"10.1109/EPTC.2016.7861517","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861517","url":null,"abstract":"In this paper an integrated wet process (photoresist strip and polymer removal) for through silicon vias fabricated by a Bosch process on a 300 mm single wafer tool will be discussed. A comparison between a dry and a wet post etch residue process, the impact of the physical force (induced by megasonics or spray) and the nature of the wet treatment will be given. Finally the cleanliness of the TSVs after either a dry or a wet process will be qualified electrically.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117160168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"3D-printing and electronic packaging - current status and future challenges","authors":"C. Bailey, S. Stoyanov, T. Tilford, G. Tourloukis","doi":"10.1109/EPTC.2016.7887895","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7887895","url":null,"abstract":"3D-Printing, or Additive Manufacturing, has received significant media attention during the last five years. A number of companies are now commercializing materials, design tools, and 3D-Printers and these are being used in a number of sectors for digital manufacturing including aerospace, medical, construction and consumer products. But what impact is 3D-Printing having on electronic packaging and manufacturing? Companies that produce and sell 3D-Printers as well as EDA and MCAD companies are now promoting 3D-Printing towards the electronics sector. This paper details the current status of 3D-printing for the manufacture and packaging of electronic systems, and provides some insights on how it may impact our community in the future. Challenges related to the performance and electrical behavior of printed conductive materials are discussed as they must meet or better the performance of materials currently used. And of course the overall quality and reliability of any 3D-printed electronic system must meet industry requirements. The paper will detail developments taking place in design and modelling tools and how these can be used in addressing some of these challenges.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117289556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A high efficient integrated heat dissipation systems with CNT array based heat lines and microchannel heat sink in 3D ICs","authors":"Yunna Sun, Seung-lo Lee, Qiu Xu, Jiangbo Luo, Hongfang Li, Yan Wang, G. Ding, Xiaolin Zhao","doi":"10.1109/EPTC.2016.7861574","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861574","url":null,"abstract":"This work mainly focused on the heat dissipation of the 3D integrated circulates (ICs). In order to satisfy the urgent heat dissipation needs, the optimal design of heat sink and optimized path for transmitting heat is one of the most promising and effective ways. Two methods have been proposed for solving the heat dissipation issues. First one was the optimized microchannel with pin fin integrated with the high-power chips or interposers. The influence of dimension of the pin fin on the heat dissipation was analyzed and optimized by FEM. The demotion of microchannel with the optimized pin fin achieved to more than 50 W/cm2 when fluid (water) speed was 1 m/s. The secondary was a novel heat line design with a cold end, which was composed of a copper plate containing nano arrays and pin fin. With the heat line integrated with Cu-pad connected with pin fin and CNT arrays, the temperature of hotspot has dropped by 17.89% (fluid cooling mode) and 9.95% (air cooling mode).","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115230008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Comparison of Au/Al, Cu/Al and Ag/Al in wirebonding assembly and IMC growth behavior","authors":"N. Jaafar, Eva Wai Leong Ching","doi":"10.1109/EPTC.2016.7861432","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861432","url":null,"abstract":"Currently, semiconductor packaging is using Gold (Au) wirebonding as the main connection from chip to the lead frame or substrate. Increases in Au price, causes suppliers to look at another alternative wire alloy as such Copper (Cu) wire. Cu wire is another option rather than Au wire due to Cu has higher tensile strength, better elongation and electrical and thermal conductivities. Cu wire has outstanding ball neck strength after the ball formation process [1], high-loop stability and high stiffness, which results in lower wire sweeping during encapsulation. These will lead to Cu wire able to have longer, lower loop profiles [2] and minimize wire sagging for fine and ultra-fine pitch wirebonding application. Another proposed alloy for wire bonding is Silver (Ag) wire. Ag has the best electrical and thermal conductivities compare to the three kinds of wires material. Ag wire has low Young's modulus compare to Cu and it is another option for replacing Au wire in wirebonding. In this paper, we shall discuss the three types of alloy wire in term of comparing the bonding quality. These will include the disadvantages and advantages of individual by comparing ball shear measurement. The silicon chip surface after bonding will be checked to confirm any crack observed on the bond pad surface occurred after ball shear for each type of wire. IMC growth for the three types of wire will be carried out at 175°C for 0hr to 504hrs will be discuss and the bond interface will be observed using the high power optical microscopy and scanning electron microscopy (SEM).","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115496086","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Finite element analysis of arbitrarily complex electronic devices","authors":"M. Gschwandl, P. Fuchs, Klaus Fellner, T. Antretter, T. Krivec, Tao Qi","doi":"10.1109/EPTC.2016.7861528","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861528","url":null,"abstract":"The capability and the range of functions of electronic devices have strongly developed over the last decade, while their size has significantly decreased. At the same time highlevel product reliability has become a vital requirement. However, for the backbone of the electronic devices, the printed circuit boards (PCBs) miniaturization often entails negative mechanical effects, such as local stress concentrations. Therefore, in order to meet the given performance standards, there is a strong demand for a tool as a basis for an optimized PCB design. This paper reveals a new framework for a lifetime estimation of these boards using Finite Element Analysis (FEA). The developed methodology can automatically generate FEA-models of arbitrarily complex build-ups from their design data. The methods were applied on exemplary printed circuit boards (PCBs) and the simulation results were verified using analytical models.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127024275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Copper wire bond pad/IMC interfacial layer crack study during HTSL (high temperature storage life) test","authors":"Ming-chuan Han, Miao Wang, Lidong Zhang, B. Yan, Jun Li, M. Song, V. Mathew","doi":"10.1109/EPTC.2016.7861590","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861590","url":null,"abstract":"Copper wire has been popular in these years when facing ever-increasing gold prices. The success of large scale conversion of gold to copper wire in microelectronics could achieve successfully when all the failure mechanisms that can be discerned during reliability testing. One of these mechanisms is corrosion of the contact between the copper (Cu) ball and the aluminum (Al) bond pad, consisting of various intermetallic compounds (IMCs), which are more sensitive to corrosion compared to gold (Au)-Al IMC. The occurrence of the related open circuit failures are often reported as a consequence of humidity related stress test, HAST or PCT. Most of paper has been published focusing on the mechanism of corrosion during humidity related stress test. Recently, wire bond pad/IMC interfacial layer crack issue was also found during high temperature storage test. The occurrence of the open circuit failures are also reported related to high temperature storage test. In this paper, a CMOS 90nm low k device with 66um fine pitch and 1.2um bond pad metal thickness was test vehicle to study the mechanism of IMC layer crack during high temperature storage test. First, failure analysis and control experiment were conducted on failed unit to dig out root cause. Failure analysis showed element sulphur was found on the periphery of bonded ball and under the bonded ball. The Sulphur was suspected to be root cause to the IMC layer crack. Next, an experiment was conducted to investigate the root cause. The factors cover different IMC coverage, different type of epoxy molding compound with different level of sulfur content. Wire pull, ball shear and IMC data were collected. Strip level thermal aging test at 225 degree C was also performed with recording pull strength and its failure mode. Molded units were subject to high temperature storage at 175 degree C. The cells with higher IMC coverage and molded by low sulfur content compound could pass electronic test and wire pull test post decamping without ball lifted issue. Last, confirmation run was performed with low Sulphur content reformulated molding compound. The units were subject to temperature cycle, HAST and HTSL. The test result showed the lot with IMC coverage over control limit could pass HTSL and T/C. No delamination was found post temperature cycle by SCAM check. Regarding copper wire bond pad/IMC interfacial layer crack, IMC coverage and sulfur content of epoxy molding compound should be considered seriously.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116903728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Copper ball bond recipe cliff test on two pad aluminum thicknesses","authors":"Kok Inn Hoo, E. DeJesus, P. Brown, Rachel Wynder, Alan Eddington, Stevan Hunter PhD","doi":"10.1109/EPTC.2016.7861587","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861587","url":null,"abstract":"“Cliff test” studies with thermosonic wirebond of 25μm copper (Cu) wire were done on integrated circuit pads having either 0.8μm or 3.0μm aluminum (Al) thickness to investigate the effect on intermetallic (IMC) formation and shear test results. One half of the pads had been probed, leaving relatively large and invasive probe marks, while the other pads were unprobed prior to wirebond. Manufacturing recipes already in use for Cu bonding on each pad thickness were designated as the “nominal” conditions. The so-called “USG cliff test” investigates wirebond results when changing the ultrasonic generator (USG) current away from the nominal setting, in increments of 10% difference, until a non-stick-on-pad (NSOP) condition occurs or until the ball has become so flat that a shear test cannot be performed. Experimental USG settings ranged from −40% up to +120% from nominal. NSOP occurred at −40% USG current. In separate tests, a similar “Force cliff test” changed the bond force away from nominal, in increments of 10% difference. NSOP did not occur when varying the force between −80% and +150% from nominal. Probe mark effects on Cu wirebond shear test results are evaluated for nominal Cu wirebonding conditions on both Al thicknesses.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124401941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Heat dissipation capability of package with integrated processor and 3D-stacked memory","authors":"Yong Han, F. Che, S. Lim, M. Kawano","doi":"10.1109/EPTC.2016.7861593","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861593","url":null,"abstract":"The thermal performance of 2.5D package with integrated processor and 2 memory stacks has been investigated, and 4 types of thermal lids without increasing the package footprint has been designed and evaluated. The heat dissipation capabilities of different structures were first analyzed under natural convection condition, and then forced air cooling condition was considered in portable device scenario. The effect of stiffener on the heat dissipation and thermal crosstalk has been analyzed. Under natural convection, providing heating power to both processor and memory, a total power around 3W can be dissipated. With forced air cooling in limited space, the initial package can dissipate around 6.5W heating power. By using the designed thermal lid, the dissipated heating power can be increased by almost one time. The results and conclusions obtained will aid the thermal design of 2.5D package.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126261725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Packaging solution for a novel silicon-based trace humidity sensor using coulometric method","authors":"P. Mackowiak, B. Mukhopadhyay, O. Ehrmann, K. Lang, M. Woratz, P. Herrmann, O. Pohl, V. Noack, Suyao Zhou, Q. Dao, T. H. Hoang, H. Ngo","doi":"10.1109/EPTC.2016.7861504","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861504","url":null,"abstract":"For a large number of industrial, technical processes and in aerospace science, the monitoring and control of water content of solid, liquid, or gaseous materials is a central and quality determining task [1]. In this paper we present our work on development of a humidity sensor array for detecting of absolute trace humidity using Pt-P2O5 electrolytic cells. Many sensor solutions on the market are using this material system for detecting of humidity. Disadvantages of these systems are their non-ability to monitor the absolute amount of water in air and their limited robustness and redundancy. One of important focuses in this work is the development of a robust and stable package for the developed sensor system. The package has to protect the sensors from surrounding, but has to provide the interface between the sensor surface and the atmosphere and a sensor electrical interface for electronics. For a reliable detection of humidity in air, a constant and laminar flow over the sensor surface is needed. The system is containing 4 sensors (cells) in a row, which allows detection of total water in the air. Our realized sensor system shows a high reliable and accurate behavior and is suitable for use in aerospace and industry [2].","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"2023 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114916396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}