Wire bond scalable design methodology

Fee Wah Chong, Yee Huan Yew
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Abstract

From the aspect of package design, when ASIC and FPGA are compared, the considerations are vastly different. FPGA design cycle is short and crucial time to market to supports multiple application domains and the package matrix needs to have vertical and horizontal migration. Hence, FPGA package designs need to have scalable design concept to drive short design cycle time for comparatively fast market turn-around time. Scalable design concept is a “Lego” brick approach whereby the module design could be leverage across vertical and horizontal migration of the package matrix. Besides improving the design efficiency, it'll also drive consistent performance across migration packages. To meet cost and resource effectiveness in low cost package, a new scalable design methodology is developed and established. This paper presents the scalable design methodology in wire bond package which involved a new design methodology and process flow in die pad assignment, wire bonding, bond finger placement and ball assignment. The challenges in die-package co-development requirements for the wire bond scalable design concept implementation will be discussed. The advantages and disadvantages of proposed design methodology comparing to conventional design approach from the aspect of design and performance will be studied. In summary, a more efficient scalable design methodology for at least 40% design efficiency improvement was proposed. This new methodology will help to increase the throughput to meet the short time to market for the FPGA package solutions.
线键可伸缩设计方法
从封装设计的角度来看,当ASIC和FPGA进行比较时,考虑的因素有很大的不同。FPGA设计周期短,上市时间关键,支持多个应用领域和封装矩阵需要有垂直和水平迁移。因此,FPGA封装设计需要具有可扩展的设计概念,以驱动较短的设计周期时间,以实现相对较快的市场周转时间。可扩展设计概念是一种“乐高”砖块方法,通过这种方法,模块设计可以跨封装矩阵的垂直和水平迁移进行利用。除了提高设计效率之外,它还将推动跨迁移包的一致性能。为了满足低成本封装的成本和资源效益,开发并建立了一种新的可扩展设计方法。本文提出了一种可扩展的线键合封装设计方法,该方法涉及一种新的设计方法和工艺流程,包括模垫分配、线键合、键合手指放置和球分配。将讨论线键可扩展设计概念实现的模封装共同开发要求中的挑战。将从设计和性能方面研究所提出的设计方法与传统设计方法相比的优点和缺点。总之,提出了一种更有效的可扩展设计方法,可将设计效率提高至少40%。这种新方法将有助于提高吞吐量,以满足FPGA封装解决方案的短上市时间。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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