2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)最新文献

{"title":"A new structure & fabrication of a high dissipation 3D package with flexible substrate","authors":"Garry Ge, G. Lye, Sonder Wang","doi":"10.1109/EPTC.2016.7861451","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861451","url":null,"abstract":"In this paper, a novel HT (high thermal) 3D package structure with 5-side heatsinks is designed to enhance, if not resolve, the heat dissipation capability constraints as encountered by current conventional stacked dies 3D package. This new package not only improves on current 3D package thermal constraints, but also can be easily implemented with low cost 2 layer flexible substrate design. So such HT 3D package feasibility study was also discussed in this paper. Through flexible substrate application, it does not involve too much tooling investment, as this HT 3D package can be easily realized via current available processes and equipment with minimal changes. With the ability to dissipate heat through 5 sides of heatsinks for this HT 3D package, higher heat dissipation than that of a conventional stacked 3D package can be achieved. In order to verify the thermal performance, thermal simulations were carried out using a commercially available CFD tool, FloTHERM©. 4 types of 3D packages were modelled. Through comparison made to conventional 5-die stacked package, this 3D package has the capability to handle 23–38% of additional package power.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133788525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A way for measuring the temperature transients of capacitors","authors":"Z. Sárkány, M. Rencz","doi":"10.1109/EPTC.2016.7861594","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861594","url":null,"abstract":"The thermal management is important not only for semiconductor components, but for discrete capacitors as well. In this paper a new measurement setup is presented that adopts the thermal transient measurement technique for capacitor components. The measurement method is demonstrated on a through-hole ceramic capacitor and validated using CFD simulations. It is also shown that using the structure function the simulation model parameters can be fine-tuned to provide a transient response that is matching the measured data.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134312560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Different conservation laws utilized for warpage prediction of MUF FCCSP with 4L ETS","authors":"Chih-Sung Chen, N. Kao, D. Jiang","doi":"10.1109/EPTC.2016.7861496","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861496","url":null,"abstract":"While the density of copper line pitch of substrate has faced a significant challenge, such as photo resist mold of 20μm pitch line, for manufacturers over the past decade, the subtractive method can be overcome by using semi-additive method. However, subtractive method is cost effective and most widely used on copper line formation, and then an emergent need of a significant change at substrate level is developed to improve both production yield and capability. As a result, embedded trace substrate (ETS) structure can replace the semi-additive method due to increase the adhesion between copper trace and prepreg (PP) material, especially for next generation requirement on further fine design of line / space (L/S). Thermal induced stress utilized to design warpage of ETS package in manufacturing process, especially for unsymmetrical structure, are becoming increasingly important due to every more stringent electronic product requirements. Although the effect of time-dependent properties can be further aggravated in glass transition temperature (Tg) neighborhood especially for epoxy molding compound (EMC), sometimes it can be neglected due to many process temperatures of component assembly is not time-dependent process and difference in a few seconds in general. In recent years, the temperature-dependent properties based on strain-, strain-stress, and stress-conservation laws has become a vital and effective methodologies for electronic package design to offer sufficient insight and understand about the warpage behavior during reflow process. Furthermore, the FEA (Finite Element Analysis) is capable of mathematically simulation irregular, complex geometry, thus an accurate and rapid methodology are thirsted for engineers in manufacturing factory due to less time-consuming and manpower-loading. In this paper, a non-incremental solution based on stress conservation law has been developed, and then processing model can been derived continuously in non-incremental formula. Different to past methodologies which non-incremental and incremental solutions are only responsible to strain and strain-stress conservation laws, respectively. In FEA for the former, element birth and death utilized in processing model can be treated as non-increment solution by assigning different reference temperatures (Tref) associated to different materials, where mean of CTE (CTEmean) can be obtained by average dimension change integrated from Tref to uniform temperature (Tuni). For the later, incremental solution utilized to perform temperature-dependent properties associated to package composite in each temperature span, and then to superpose nodal displacement of each temperature span as global and local analysis. Compare to incremental solution, although non-incremental solution based on strain conservation is not popular but also save time calculated by professional computer, especially for high density or fine increment of data described in temperature-dependent properti","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"398 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123801734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High efficiency energy harvesting circuit with impedance matched antenna","authors":"Y. Shinki, Kyouhei Shibata, M. Mansour, H. Kanaya","doi":"10.1109/EPTC.2016.7861536","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861536","url":null,"abstract":"This paper describes the design of a high efficiency energy harvesting circuit combined with antenna. The circuit is composed of a series resonance circuit and boosting rectifier circuit for converting radio frequency power into a DC boosted voltage. For further efficiency improvement, input impedance of antenna is optimized. The simulated output DC voltage is 9.0V for an input of 100mV at 900MHz.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122264731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Ultra-fine pitch Cu-Cu bonding of 6μm bump pitch for 2.5D application","authors":"S. Chong, Ling Xie, S. Wickramanayaka, V. N. Sekhar, Daniel Ismael Cereno","doi":"10.1109/EPTC.2016.7861452","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861452","url":null,"abstract":"Ultra-fine pitch (6μm) interconnects are essential for high-end application-products that demands high speed and high bandwidth inter-chip communication. Achieving Cu-Cu bonding with such a fine pitch is challenging since bond time is too long and bond interface gets easily oxidized. Throughput issue associated with long-bonding time is solved by using 2-step bonding procedure where first step is a temporary bonding and second step is a permanent bonding using a gang bonder. Gaseous formic acid is used to remove surface oxide on Cu surface and wafer level pre applied underfill is used as a tacking material in temporary bonding. Bonding is carried out with dies having 500,000 interconnects and the results show excellent bonding and electrical properties.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"2012 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127382510","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Molding process development for high density I/Os Fan-Out Wafer Level Package (FOWLP) with fine pitch RDL","authors":"M. Ding, S. Chong, D. Ho, S. Lim","doi":"10.1109/EPTC.2016.7861433","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861433","url":null,"abstract":"With the perpetual demand for greater functionalities, better performance and greater energy efficiency at cheaper manufacturing cost and smaller form factor, Fan-Out Wafer Level Packaging (FOWLP) technology has emerged as one of the most promising technology in fulfilling the demands from electronic devices for mobile and network applications. In our FOWLP mold-first approach development work, we developed the 300mm compression molding process for high density input/output (IO)s reconstituted FOWLP mold wafer fabricated with fine pitch redistributed layer (RDL) of line width / line space (LW/LS) ≤5/5μm using the conventional mold-first approach. Our compression molding process development aims to achieve a chip-to-mold non planarity ≤3μm, warpage of reconstituted FOWLP mold wafer ≤1mm and wafer level die shift ≤10μm. In this paper, we will discuss on the 300mm compression molding development work like materials selection, pick-and-place (PnP) process parameters and die shift compensation via constant and dynamic pre-shift methodologies in achieving our targeted specifications for the fabrication of fine pitch RDL FOWLP.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127711149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fabrication process of a triple-layer stacked TSV interposer for switch matrix consisting of eight RF chips","authors":"Wei Meng, Y. Guan, Qinghua Zeng, J. Chen, Yufeng Jin","doi":"10.1109/EPTC.2016.7861564","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861564","url":null,"abstract":"This paper presents one fabrication process of a triple-layer stacked TSV interposer for switch matrix consisting of eight RF chips. There are about 600 TSVs in the interposer and the diameter of TSV is 40um with the aspect ratio being 4:1. The whole area of the interposer is 13.5 mm × 7.5mm and the thickness of the triple-layer stacked interposer is only about 0.7mm. After the process, the electrical properties of RDL and TSV on the interposer are tested and the transmission losses of them are only about 0.2dB and 1.39dB at 4GHz, respectively.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129531535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Manufacturing and characterization of die to die interconnections for 3D applications in harsh environmental conditions","authors":"C. Hartler, J. Siegert, F. Schrank, M. Schrems, Z. Hajdarevic, S. Bulacher","doi":"10.1109/EPTC.2016.7861546","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861546","url":null,"abstract":"Key end user applications, such as Internet of Things (IoT), automotive, mobile internet and wearable devices, require smaller, denser and more complex packages with increased performance, all at a low power usage. Innovative front end technologies enabling transistor downscaling towards 10 nm pave the way for small pitch components with an increased I/O count, thus leading to a packaging technology revolution from simple wire bond assembly over BGA/flip chip applications towards stacked 3D-structures with through silicon vias (TSVs), micro bumps and thin dies. 3D die to wafer (D2W) stacking therefore becomes an essential and cost effective option in order to further optimize the form factor. Moreover, by stacking components onto each other instead of placing them next to each other, performance increases can be obtained due to shorter signal paths and higher possible frequencies. The work described in this paper elaborates flip chip stacking processes in combination with TSV technology for More-than-Moore (MtM) heterogeneous 3D-Wafer-Level-Chip-Scale-Package (WLCSP) integration, targeting applications in harsh environments with high demands on product reliability. The major objective comprises the proof of manufacturability at competitive costs. In addition the devices were tested against harsh automotive conditions that are present near the alternator, featuring high temperatures up to 200 °C.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126473259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Gas Chromatography Mass Spectrometry (GC-MS) application in back end semiconductor: Chemical cleaning efficiency assessment","authors":"L. Ying, Lim Koo Foong","doi":"10.1109/EPTC.2016.7861503","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861503","url":null,"abstract":"In comparison to GC-MS applications in semiconductor front end (wafer fabrication), this technique seems to have fewer applications in semiconductor back end (package assembly processes assessment. In this work, GC-MS is applied in a different analysis approach for cleaning efficiency assessment in one of the back end processes. This analysis approach is proposed, executed, assessed, improved and finally reported with positive results in the characterization method of cleaning quality using packages from back end processes. A unique sample preparation method is introduced in this assessment to collect solution which is dissolved from the entire external package surfaces and enables GC-MS analysis. Inclusion of reference as standard in this GC-MS analysis approach is crucial to ensure conclusive results of cleaning efficiency assessment.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122939937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Defects in nickel plating layers on copper-metallized substrates induced by thermal cycles","authors":"S. Fukuda, K. Shimada, N. Izu, H. Miyazaki, Shoji Iwakiri, K. Hirao","doi":"10.1109/EPTC.2016.7861431","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861431","url":null,"abstract":"The reliability of electronic substrates at high temperature is a significant issue for high-power semiconductor modules. To improve the reliability, it is essential to understand and reduce thermal-cycling-induced surface roughening of metal layers on the substrates. We observed the surfaces and cross sections of nickel plating layers on copper-metallized silicon nitride substrates by active metal brazing after the substrates were subjected to thermal cycles of −40 to 250°C. No cracks were observed on the surfaces of the nickel layers on substrates that were subjected to 100 and 200 thermal cycles. However, voids or cavities were observed just under the nickel surfaces on those substrates. We considered that those voids or cavities were formed by thermal stress induced by thermal cycling and that they could be one of the origins of cracks in the nickel layers.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"146 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123351849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}