Fabrication process of a triple-layer stacked TSV interposer for switch matrix consisting of eight RF chips

Wei Meng, Y. Guan, Qinghua Zeng, J. Chen, Yufeng Jin
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引用次数: 1

Abstract

This paper presents one fabrication process of a triple-layer stacked TSV interposer for switch matrix consisting of eight RF chips. There are about 600 TSVs in the interposer and the diameter of TSV is 40um with the aspect ratio being 4:1. The whole area of the interposer is 13.5 mm × 7.5mm and the thickness of the triple-layer stacked interposer is only about 0.7mm. After the process, the electrical properties of RDL and TSV on the interposer are tested and the transmission losses of them are only about 0.2dB and 1.39dB at 4GHz, respectively.
由8个射频芯片组成的开关矩阵三层堆叠TSV中间层的制造工艺
本文介绍了一种由8个射频芯片组成的开关矩阵三层堆叠TSV介子的制作工艺。中间层约有600个TSV, TSV直径为40um,纵横比为4:1。中间层的整体面积为13.5 mm × 7.5mm,三层堆叠的中间层厚度仅为0.7mm左右。加工完成后,对中间插板上的RDL和TSV的电学性能进行了测试,在4GHz时,它们的传输损耗分别仅为0.2dB和1.39dB左右。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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