2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)最新文献

{"title":"Gravure printing of Ag electrodes for electroluminescent lighting","authors":"V. Sunappan","doi":"10.1109/EPTC.2016.7861549","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861549","url":null,"abstract":"Electroluminescent lighting (EL) is a form of printed lighting on flexible film processed traditionally using screen printing technique for small areas or panel sized formats. Roll to roll slot coating of EL inks (phosphor, dielectric and Ag conductor) was implemented to increase productivity for large area printed electronics applications. However, material cost remains a big concern for widespread industry adoption of printed lighting. In this work, the Ag electrode thickness on printed lighting was successfully reduced by two thirds by conversion of slot coating to gravure printing. A wide range of printing thicknesses and sheet resistivities were produced by varying gravure cell design. A minimum print thickness range of 5∼7 μm was found feasible without defects with sheet resistance of 210 Ω/sq. This was achieved by gravure cell depth of 75 μm. Printing layer thickness can be increased easily by increasing gravure cell depth. Print layer thickness under 5 μm generated porosities. The printed lighting brightness was almost unchanged by reduced electrode thickness.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"0707 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125580096","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Double side sintered IGBT 650V/ 200A in a TO-247 package for extreme performance and reliability","authors":"G. Greca, P. Salerno, J. Durham, F. Le Henaff, Jean Claude Harel, J. Hamelink, Weikun He","doi":"10.1109/EPTC.2016.7861548","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861548","url":null,"abstract":"The objective of this work is to evaluate thermal and electrical performance improvements from silver sintering compared to traditional solder attachment in an IGBT + diode / 650V rated TO-247 package. The devices under test (D.U.T) will be stressed by continually adjusting current to maintain the same delta Tj°C. After initial electrical and thermal characterization of the samples, the D.UTs were subjected to thermal and power cycling stress qualification profiles consisting of 200A 15s on, 15s off with delta Tj of 100°C and delta Tj of 85°C for the sintered parts, and 130A 15s on, 15s off with delta Tj of 85°C for the soldered parts. Thermal impedance was measured during power cycling/pulsing tests and metallographic analysis were used to evaluate potential defects on the die attach interfaces. Vce (sat) was also be measured and analysis of the impact on the devices' junction temperature and consequently on the attachment reliability will be performed.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126100116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Development of bottom-up Cu electroplating process and overburden reduction for through silicon via (TSV) application","authors":"Gilho Hwang, R. Kalaiselvan, Hilmi B Mohamed Yusoff","doi":"10.1109/EPTC.2016.7861442","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861442","url":null,"abstract":"Conventional through silicon via (TSV) Cu electroplating produces excessive Cu overburden, which is deposited on wafer surface. Cu overburden can cause wafer warpage and has to be removed by chemical mechanical polishing (CMP) for following process. We developed new approach to reduce Cu overburden by combining TSV Cu electroplating and chemical seed layer etching. Process parameters for 1st TSV Cu electroplating were optimized for partial TSV filling, followed by Cu wet etching to remove excessive Cu overburden and Cu seed layer. Solid-filled Cu TSV with reduced Cu overburden can be achieved by consecutive 2nd TSV Cu electroplating.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127835465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A design-of-experiment (DOE) to optimize a SiP design for connectivity applications","authors":"B. Qi, C. Hanna","doi":"10.1109/EPTC.2016.7861448","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861448","url":null,"abstract":"System-in-Package (SiP) is becoming more and more important in integrating functionality while reducing final product form factors and cost. This is particularly true for mobile applications where continued effort to achieve ever smaller products is continuously pushing development of new materials, components and assembly technologies. An optimization study of a SiP design based on a functional product is discussed in this presentation to address the following: 1. Design optimization to reduce component spacing with varied assembly challenges 2. Substrate stack-up optimization for z-height reduction with coreless substrate technologies 3. Flip chip (FC) bump pad optimization for ball bumped or copper-pillar bumped CMOS silicon's 4. Cost reduction potential to replace SOP with paste printing using u-stencil for flip chip applications 5. Assessment of different MUF and fluxing underfill (FU) materials To accomplish these objectives, two types of bumped silicon wafers/dice, three different substrates and four different materials were implemented in this DOE. Short-looped wafers of an actual live device were bumped with CuP pillar as well as with SnAg ball bumping technologies. All three substrate designs are coreless, as compared with the original POR conventional design. One substrate was designed with the plan-of-record (POR) component spacing on a 6-layer stack-up that results in ∼ 290 um overall z-height; X-Y-Z size reductions were achieved on the alternative 4-layer design that has reduced component spacing as well as a reduced overall z-height of ∼ 190 um; furthermore, embedded trace substrate (ETS) was used as the top layer for the 4-layer designs to ensure improved routing capabilities. Subtle differentiation between these two 4-layer designs is in the die shadow area on the top ETS layer: while one design uses solder mask defined pads (SMD) the other uses the ETS dielectric materials to define the flip chip bonding pads without solder mask (NSMD). The latter design facilitates the MUF flows for ultralow stand-off flip chip solder joints and make it a likely “universal” pad design for both CuP and SnAg flip chip bump attach. Four different MUF materials along with one FU materials were used for DOE assembly: the first MUF is the POR material currently used in HVM production with nominal filler sizes; 2nd MUF is for low warpage applications (especially for thin, coreless substrate); 3rd MUF has a smaller filler size that is optimized for small stand-off flip chip bumps and the last MUF has a much improved thermal conductivity and is assessed here for its fit-for-use in other high thermal density applications. FU used is an underfill material with build-in flux and is opportunistically included here to assess its fit for use for our future products. Overall DOE plans shall be described, preliminary results as well as the screening test plan will be presented in some detail and implication of these interacting factors in improving a SiP design","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124348416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Macro and micro-texture study for understanding whisker growth in Sn coatings","authors":"Piyush Jagtap, Praveen Kumar","doi":"10.1109/EPTC.2016.7861464","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861464","url":null,"abstract":"The current work is aimed at analyzing the effects of crystallographic texture, both macro and microtexture, on whisker growth. The macro-texture of the Sn coatings deposited on brass substrate was systematically studied by varying the process parameters used for electro-deposition. The combination of process parameters, such as deposition temperature and current density, and the resulting macro-texture most prone to whisker growth were identified by monitoring the whisker growth in Sn coatings. The electron back-scatter diffraction (EBSD) technique was then used to identify the grains where whiskers actually grow. Both macro- and micro-texture of Sn coatings revealed that coatings with pre-dominant low Miller index grain orientations, such as (100), were highly susceptible for whisker growth. Whisker propensity decreased as the texture transitioned from low to high Miller index grain orientation. The microtexture mapping of the Sn coatings using EBSD technique confirmed that whisker grows from low Miller index grains with (100) or near (100) orientations, surrounded by grains of similar orientation followed by grains with high index plane grains, such as (211), (210) or (321). This particular double ring configuration along with local stress field can be used to predict the locations for whisker growth.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124773151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"MEMS WLCSP development using vertical interconnection","authors":"B. Jung, C. Zhaohui, Bu Lin, D. Zhi, D. Peng, C. T. Chong","doi":"10.1109/EPTC.2016.7861520","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861520","url":null,"abstract":"As the demand of MEMS device in mobile application is increased, MEMS device packaging technology is facing to the challenge to reduce the size and thickness. One of promising packaging solution to overcome this challenge is WLCSP (Wafer Level Chip Scale Package) using TSV(Through Silicon Via)[1,2,3]. A WLCSP using TSV technology is able to provide the smaller form factor as this used a vertical interconnection through Si die instead of conventional wire bonding for interconnection between Si die and substrate. However TSV process is still limited to apply various products since it has higher process and material cost compare to conventional wire bonding package. This study proposes a novel cost effective MEMS WLCSP using Si pillar structure and Cu wire, which work as a vertical interconnection to reduce the package size and thickness. This structure is able to provide a lower cost than TSV process since separate expensive process such as DRIE and Cu filling, etc. is not required to form the vertical interconnection. As a bottom MEMS device, 2D — accelerometer device was used in this study, and cap wafer was bonded on bottom wafer using Al-Ge eutectic bonding with wafer to wafer bonding technology. In this study, different EMCs were evaluated to optimize the package structure in the view point of process such as warpage, void and EMC filling in the gap. Also parametric study of mechanical simulation is performed to predict the stress level of MEMS device with process flow and package thickness.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122168059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Ultrasonic power closed-loop control on wire bonder","authors":"He Yunbo, Hu Yongshan, Chen Xin, Gao Jian, Y. Zhijun, Zhang Kai, Chen Yun, Zhang Yu, Tang Hui, Ao Yinhui","doi":"10.1109/EPTC.2016.7861570","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861570","url":null,"abstract":"Ultrasonic is one important factor of ultrasonic wire bonding process, which is widely used in semiconductor packaging industry. Control effect of ultrasonic power determines the quality and speed of wire bonding. Based on analysis of ultrasonic frequency characteristics and current response, this paper proposes a closed-loop control method of automatic frequency tracking and output current control, to improve the effectiveness of ultrasonic power, shorten the response time, and enhance the stability of ultrasonic generation. Automatic frequency tracking is based on phase lock method. Phase difference of voltage and current signals works as the feedback of the close-loop control of frequency to realize automatic frequency tracking and ensure that the ultrasonic transducer always works at resonance point. And output current control is working at constant current mode so that the vibration amplitude of ultrasonic can be better controlled by adjusting the ultrasonic current. The experimental results show that with the frequency automatic tracking method, the ultrasonic transducer system can achieve wider frequency bands, with faster phase locking and higher tracking precision. With close loop control, real-time tracking can be realized and less rise time and less overshoot of ultrasonic current can be achieved.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115114918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Effect of mechanical properties of the ceramic substrate on the thermal fatigue of Cu metallized ceramic substrates","authors":"H. Miyazaki, Shoji Iwakiri, H. Hirotsuru, S. Fukuda, K. Hirao, Hideki Hyuga","doi":"10.1109/EPTC.2016.7861486","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861486","url":null,"abstract":"The effects of temperature cycling from −40°C to 250°C on the active metal brazing (AMB) substrates were investigated using silicon nitride ceramics or aluminum nitride ceramics with different fracture toughness and strength. Visual inspection of the substrates after 1000 cycles hardly detected failure in the Si<inf>3</inf>N<inf>4</inf>-AMB substrates with the high fracture toughness of 8.0 MPa·m^1/2. By contrast, the Si<inf>3</inf>N<inf>4</inf>-AMB substrates with the lower fracture toughness of ca. 5 MPa·m^1/2 exhibited delamination of the Cu layer at only 20 or 50 thermal cycles. Detachment of the Cu layer occurred at seven cycles when the AlN-AMB substrates with fracture toughness of 3.2 MPa·m^1/2 were employed. It was found that the endurance to thermal fatigue of AMB substrates was controlled by the fracture toughness of ceramic substrates rather than the fracture strength.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130871537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Modeling of the effect of heat flux on replication accuracy using roll-to-roll micro hot embossing","authors":"S. Chen, X. Shan, H. S. Ng, Zhaowei Zhong, B. M. Mohaime","doi":"10.1109/EPTC.2016.7861472","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861472","url":null,"abstract":"R2R large area fabrication of functional panels gained popularity in recent years and micro 3D profiles for optical films and biomedical applications have gained momentum with improving replication accuracies in hot embossing systems. However, studies on the effect of heat flux on the replication accuracy have been lacking. In this study, a twin belt based roll-to-roll embossing system was designed and built to study the effects of various in-situ heat transfer at the hot embossing nip. Seamless embossing was then demonstrated on PVC film. The effects of different heat transfer schemes have been modeled using Solidworks simulation applying experimentally obtained mechanical properties of the polymer film. The simulation results are compared quantitatively to the experimental results to analyze the effect of heat transfer schemes on the replication accuracies. We achieved 92% replication accuracies on the PVC film replicated by application of heat on the side of the film not in contact with the mold. It is significantly higher than the features replicated using an isothermal condition at Tg and also heat transfer from the mold. Thermal simulation shows a steep thermal gradient between the polymer under nip and the immediate surrounding for the isothermal conditions and a gentle thermal gradient for the other two schemes. Displacement of the polymer shows a highest flow of material from the surrounding of the feature for the underside heating method. This results in a more accurate replication onto the PVC film.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133659034","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Modelling solder extrusion using J-integral method","authors":"C. Selvanayagam, Teng Di Sheng","doi":"10.1109/EPTC.2016.7861578","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861578","url":null,"abstract":"Solder extrusion is a phenomenon where molten solder fills a crack in the solder resist during reflow, causing a short failure. FEA was used to first understand this phenomenon, and then investigate the effect of die warpage, presence of stacked via and substrate CTE on solder extrusion risk. A 2D crack propagation model was developed. This model assumes the presence of an initial crack and calculates the propensity of the crack to grow using the J-integral method. The J-integral is equivalent to the energy release rate. Fracture can be predicted by comparing calculated values of J-integral to a critical value for the material being evaluated. This work is important because in the future it can be extended to predict solder extrusion risk before the first packages are built, taking into account factors such as stacked vias, copper plane placements, substrate material properties, size, and warpage. In addition, this model can be used to optimize locations of 3-stack vias and copper planes, in compliance with electrical design.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114554313","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}