MEMS WLCSP development using vertical interconnection

As the demand of MEMS device in mobile application is increased, MEMS device packaging technology is facing to the challenge to reduce the size and thickness. One of promising packaging solution to overcome this challenge is WLCSP (Wafer Level Chip Scale Package) using TSV(Through Silicon Via)[1,2,3]. A WLCSP using TSV technology is able to provide the smaller form factor as this used a vertical interconnection through Si die instead of conventional wire bonding for interconnection between Si die and substrate. However TSV process is still limited to apply various products since it has higher process and material cost compare to conventional wire bonding package. This study proposes a novel cost effective MEMS WLCSP using Si pillar structure and Cu wire, which work as a vertical interconnection to reduce the package size and thickness. This structure is able to provide a lower cost than TSV process since separate expensive process such as DRIE and Cu filling, etc. is not required to form the vertical interconnection. As a bottom MEMS device, 2D — accelerometer device was used in this study, and cap wafer was bonded on bottom wafer using Al-Ge eutectic bonding with wafer to wafer bonding technology. In this study, different EMCs were evaluated to optimize the package structure in the view point of process such as warpage, void and EMC filling in the gap. Also parametric study of mechanical simulation is performed to predict the stress level of MEMS device with process flow and package thickness.