{"title":"Modelling solder extrusion using J-integral method","authors":"C. Selvanayagam, Teng Di Sheng","doi":"10.1109/EPTC.2016.7861578","DOIUrl":null,"url":null,"abstract":"Solder extrusion is a phenomenon where molten solder fills a crack in the solder resist during reflow, causing a short failure. FEA was used to first understand this phenomenon, and then investigate the effect of die warpage, presence of stacked via and substrate CTE on solder extrusion risk. A 2D crack propagation model was developed. This model assumes the presence of an initial crack and calculates the propensity of the crack to grow using the J-integral method. The J-integral is equivalent to the energy release rate. Fracture can be predicted by comparing calculated values of J-integral to a critical value for the material being evaluated. This work is important because in the future it can be extended to predict solder extrusion risk before the first packages are built, taking into account factors such as stacked vias, copper plane placements, substrate material properties, size, and warpage. In addition, this model can be used to optimize locations of 3-stack vias and copper planes, in compliance with electrical design.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EPTC.2016.7861578","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
Solder extrusion is a phenomenon where molten solder fills a crack in the solder resist during reflow, causing a short failure. FEA was used to first understand this phenomenon, and then investigate the effect of die warpage, presence of stacked via and substrate CTE on solder extrusion risk. A 2D crack propagation model was developed. This model assumes the presence of an initial crack and calculates the propensity of the crack to grow using the J-integral method. The J-integral is equivalent to the energy release rate. Fracture can be predicted by comparing calculated values of J-integral to a critical value for the material being evaluated. This work is important because in the future it can be extended to predict solder extrusion risk before the first packages are built, taking into account factors such as stacked vias, copper plane placements, substrate material properties, size, and warpage. In addition, this model can be used to optimize locations of 3-stack vias and copper planes, in compliance with electrical design.