2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)最新文献

{"title":"Evaluation of printed heating elements for continuous flow PCR application","authors":"W. Fan, B. Lok, F. K. Lai","doi":"10.1109/EPTC.2016.7861505","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861505","url":null,"abstract":"Printed electronics on flexible substrate is becoming more popular in the flexible and wearable products for biomedical, lab-on-chip and automotive. Flexible printed passive components (resistance, inductance and capacitance) are an attractive solution to the hybrid passives on polymer substrate. Printed resistor can be used as normal resistor, thermistor and heater through the selection of different conductive and resistive materials. The evaluation of printed 3-zone heating elements for continuous flow PCR (polymerase chain reaction) application will be studied in this study.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127302515","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High lead solder failure and microstructure analysis in die attach power discrete packages","authors":"Kenny Chiong, HongWen Zhang, S. Lim","doi":"10.1109/EPTC.2016.7861539","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861539","url":null,"abstract":"High lead solder has a long history of use in the semiconductor industry as a die attach and interconnect material within high-current-density discrete power packages. The main reason high Pb solder is still an ideal material and cannot be replaceable until today because of its low resistance, high thermal conductivity for improved electrical performance, ductility to accommodate thermal expansion mismatches between joining materials, and a high melting temperature to sustain multiple reflow cycles. Typical high Pb die-attach materials are PbSn, PbSnAg or PbInAg alloys with the formation of intermetallic compounds which builds an adhesion layer between substrate or die metallization and bulk solder is critical for giving a strong reliable joint. Both Ag3Sn and Cu3Sn IMC layer are the common interface formation for TiNiAg backside die metallization on bare Cu leadframe. IMC interface Ag3Sn layer spalling with discrete structure embedded in the Cu3Sn IMC on the die side is not desirable as it may weaken the interface structure and thus leading to solder crack formation. It can happen at both the die side as well as Cu lead side. Spalling is associated with (1) the Sn content inside the solder, (2) the reflow profile being used (over heating). The overleaching Cu and the formation of Cu3Sn or Cu-rich particles inside the joint or even along the Ag3Sn layer at die side would make the joint harder and more brittle. In fact, vertical crack and the localized circular crack at the SiC die top was found right beneath the clip dimple during the reflow process. The localized circular cracking right beneath the dimple clip indicates a compression stress there along X and Y directions. Meanwhile, the vertical crack indicates the tensile stress along the X and Y directions inside the die. The CTE match between the substrate and Die or the clip and Die may warp the Si die. The hardened solder did not absorb the strain caused by the CTE mismatch and finally the stress from the mismatch strain lead to the crack of the Si die. The focus of this study is to investigate the die cracking and correlation between the BLT and IMC thickness formation will be explored as a part of this study as well throughout a series of DOEs performed to characterize the reflow process.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133613956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A halogen-free epoxy with intrinsic flame retardance for use in electronic packaging","authors":"Song Kiat Jacob Lim, Jian Rong Eric Phua, Yu Bai, Xiao Hu, C. Gan","doi":"10.1109/EPTC.2016.7861500","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861500","url":null,"abstract":"Typical epoxy-based electronic packaging materials necessitate substantial inclusion of flame retardant additives in order to satisfy regulatory requirements regarding flammability, usually evaluated by the UL-94 flammability test. Conventional additives such as encapsulated red phosphorus may pose a reliability issue under high humidity environment due to its hygroscopic nature, leading to electrical shorts caused by electrochemical migration. A non-halogenated epoxy based on the Polyhedral Oligomeric Silsesquioxane (POSS) structure possess inherent flame retardance and excellent high temperature properties. This study investigate the feasibility of utilizing POSS-based epoxy to replace conventional epoxies as an intrinsically flame retardant electronic packaging materials with enhanced reliability.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117207545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Influence of package lead type onto final test contacting","authors":"Praveen Kumar Ramamoorthy, T. H. Guan, A. Yeo, Yang Kai","doi":"10.1109/EPTC.2016.7861554","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861554","url":null,"abstract":"As per the requirements of the market, current semiconductor trend is towards shrinking packages thereby reducing package dimensions. This in turn results in reduced lead pitch and width giving less space for contacting during final testing. Another trend recently observed for the package lead is the shift from matteSn plating towards preplated leadframes or otherwise called uPPF. When it comes to power testing requirements like kelvin testing that needs to have two contacts on single lead this shift is a challenge for contacting. This paper discusses in detail the observations of the difference in the material interaction between pin and the two different leadframes at constant current flowing through the pin.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131561370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Evolution of structured adhesive wafer to wafer bonding enabled by laser direct patterning of polymer resins","authors":"K. Zoschke, K. Lang","doi":"10.1109/EPTC.2016.7861476","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861476","url":null,"abstract":"The paper reviews structuring methods of adhesive layers which can be subsequently used for thermo-compression type wafer to wafer bonding processes. With respect to limitations of the state-of-the-art adhesive structuring approaches laser direct patterning of polymer resins is introduced. The process features a 248 nm excimer laser stepper with mask based pattern projection and high speed XY-moving stage. Non-cured polymer precursors such as Cyclotene™ resins can be well structured with this direct ablation method. As additional feature of the new structuring method patterning of polymer compound layers is introduced and discussed. This approach enables structuring of polymer layer stacks having different cure conditions enabling adjusted material flow and squeeze capabilities in subsequent wafer bonding processes. The experimental setups as well as the results of structuring and bonding trials with different polymer layers are discussed in this work.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128314107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Novel correctable testing interface for high speed/frequency device testing","authors":"Chih-Cheng Chuang, Kuan-I Cheng, S. Wu, Lung-Shu Huang, Bang-Cheng Chiu","doi":"10.1109/EPTC.2016.7861571","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861571","url":null,"abstract":"The socket is regarded as a testing interface. It can measure the performance of package and fix the signal path from ATE to DUT (Device under Test). With testing frequency getting higher and higher, it will cause SI (Signal Integrity) problem when testing. The signal can't transmit completely with high frequency because of the excessive loss. Therefore, to solve this problem, use de-embedding method to remove effects caused by the socket and the load board. To simplify these complicated steps, this paper proposes the calibration kits to apply on the socket especially. Move the reference plane from the two sides of the load board to the tip of pogo pins. And use SOLT calibration method to have a standard definition table. As a result, tester can use this table to extract the error from tester and signal path and the error can be modified. In this way, tester can measure the performance of DUT directly.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"39 12","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133170725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Key parameters influencing Cu-Sn interfacial void formation","authors":"G. Ross, V. Vuorinen, M. Paulasto-Kröckel","doi":"10.1109/EPTC.2016.7861521","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861521","url":null,"abstract":"Recent trends in 3D integration and dimensional scaling technologies have attracted interest in micro-connects as a novel method for interconnection. Micro-connects, including small volume interconnects (or microbumps) and Solid Liquid Interdiffusion (SLID) bonds for Micro- or Nanoelectromechanical Systems (MEMS and NEMS) are functionally far superior compared with traditional large volume interconnects and enable novel integration techniques for the miniaturisation and diversification of complex integrated systems. As micro-connects have smaller volumes than traditional forms of interconnects, they become more susceptible to microstructural defects. Such defects can lead to the catastrophic and costly failures within complex integrated systems. This study of Cu-Sn micro-connects has resulted from the publishing of several papers on the reliability reduction with interfacial voiding cited as the root cause. Interfacial voids (often referred to as Kirkendall voids) form in micro-connects fabricated using electroplated Cu in contact with the low melting point metal Sn. A variety of Cu electroplating chemistries and current densities were used to assess the void formation characteristics and the resulting IMC growth rates. The variety of parameters is designed to assess the impacts on void formation. This data will enable electronic integration developers to better understand the reliability impacts and for manufactures to understand key parameters associated with void formation.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133512304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thermal management of high performance test socket for wafer level package","authors":"Yong Han, Seow Meng Low, J. Goh","doi":"10.1109/EPTC.2016.7861436","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861436","url":null,"abstract":"High performance test sockets with thermal management solutions have been developed for wafer level package of high power. Three types of active cooling solutions have been designed and integrated in the test socket. Type A of more compact size can be easily assembled in the space limited environment. Type B is much larger and more complex, including 4 direct touch copper heat pipes. Type C comprises of direct contact liquid cooler for chip heat delivery and outside exchanger for heat rejection to the environment. To maintain the maximum chip temperature under 85°C, the heating power of around 80W and 120W can be dissipated with type A and type B respectively. With Type C, the dissipated heating power can be as high as 150W. Appropriate management of test socket thermal issue will assure the success for high performance test of advanced packages.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132047885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Large area roll-to-roll screen printing of electrically conductive circuitries","authors":"B. Salam, X. Shan, Wei Jun","doi":"10.1109/EPTC.2016.7861481","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861481","url":null,"abstract":"In this study, the roll-to-roll equipment was used to print up to 1000 mm web width and 400mm repeat length. Two screen types, 275 and 325 inch-per-line (ipl) mesh, were studied. The 275 inch-per-line mesh plate has 39 μm opening, 53 μm non-opening, and 83 μm thick and the 325 ipl mesh plate has 30 μm opening, 48 μm non-opening, and 65 μm thick. These screen mesh specifications indicate that the 325 screen mesh is meant for printing relatively finer and thinner patterns, compared to the 275 screen mesh. Printing using the studied screens was conducted using lenticular test patterns and RFID patterns. The remaining printing parameters such as squeegee, attack angle, web speed, substrate, ink, and drying temperature, were kept same for both screens. The study found that the investigated high-count-mesh screen can print fine patterns up to 108 μm and the studied low-count-mesh screen can print coarser patterns of above 150 μm with relatively thicker patterns of 10 μm. The printing uniformity was also characterized by measuring the electrical resistance values. The results show that the electrical resistance values have deviation of below 10% from the average resistance value.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"780 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127771847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Isolate micro-bump process development and improvement","authors":"H. Li, Leong Yew Wing, Hwang Gilho, Chong Kok Piau, N. Jaafar, S. Chungpaiboonpatana","doi":"10.1109/EPTC.2016.7861581","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861581","url":null,"abstract":"Low density micro-bumps were required for assembly of different technologies connection within 3D and 2.5D packaging. 6μm and 8um bump heights after reflow are required for 15μm and 25μm (Cu/SnAg) diameter micro-bump, respectively. At same time, the pattern density of 15um and 25μm diameter micro-bump are 0.045% and 0.127%. This paper reported the process challenges, evaluation and development. The average test yields after process development and optimization for 25μm and 15μm micro-bump are 94.5% and 47.5%, respectively.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129160543","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}