2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)最新文献

{"title":"Copper circuit traces by laser cladding with powder injection for additive manufactured mechatronic devices","authors":"M. Mueller, O. Hentschel, M. Schmidt, J. Franke","doi":"10.1109/EPTC.2016.7861551","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861551","url":null,"abstract":"Laser cladding allows for a fast, flexible and direct plotting of electric conductive structures on polymer based substrates. The surface of the substrate is selectively melted by a focused laser beam. Simultaneously, a metal powder is lead through a powder nozzle. This nozzle is oriented laterally or coaxially to the laser beam. As a result, a molten bath of substrate and powder material is created. After cooling and solidification a welding bead on the substrate surface is formed. With this generation of circuit traces mechatronic devices can be built up, especially for high current power electronic applications. In this paper copper circuit traces on polymere substrates, produced by laser cladding with powder injection are characterized for their optical, electrical and mechanical properties by measuring resistance, adhesive strengths and current-carrying capacity including the effects of simulated environmental influences.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125232243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Novel WLCSP technology solution for fusion device of CMOS integrated circuit with MEMS","authors":"T. Murayama, T. Sakuishi, Y. Morikawa","doi":"10.1109/EPTC.2016.7861541","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861541","url":null,"abstract":"For the realization of the IoT (Internet of Things) society where the arrival is strongly predicted soon, the construction of an intelligent sensor network is important. For such a sensor network construction, the enormous numerical fusion devices that CMOS devices and MEMS sensors are integrated are essential. To develop WLCSP (Wafer Level Chip Size Packaging) technologies as high density packaging technology for mass production of the high reliability and low-cost devices, improving performance and downsizing of these devices, is important including novel process integration. Considering new integration of WLCSP in future, it is considered necessary to develop DRIE (Deep Reactive Ion Etching) technology for etching Si, mold, metal and insulator, or heterogeneous sacks of these materials. We have developed Non-Bosch “scallop-free” etching method for Si DRIE in our original high density NLD (magnetic Neutral Loop Discharge) plasma. [1] In this work, the first trial of Bosch etching was conducted using same plasma source of Non-Bosch. It is quietly important to control atmosphere of the sealed cavity with MEMS, there is a possibility that higher-quality controlling technology for atmosphere of sealed cavity is required with WLCSP evolution in future. Conventional MEMS etching method is Bosch etching. In Bosch method, Si is etched to anisotropic profile by using fluorine radical reaction to Si, and sidewall passivation of fluorocarbon polymer. [2] Due to such etch reaction mechanism, the residues of fluorine and fluorocarbon exist on etched surface, it is possible that these residual will have a negative impact to the cavity atmosphere after sealed. In this paper, as a part of the data acquisition to consider about the management standard of the sealed cavity atmosphere, we started comparison between Bosch and Non-Bosch to investigate whether influence of Si etching method influence to sealed cavity atmosphere or not. In this work, each sample of Bosch and Non-Bosch sample was prepared using by NLD plasma etcher, then, TDS (Thermal Desorption Spectroscopy) analyses were carried out to detect desorption species from etched surface of sample. TDS analyses were conducted each process step; after Si etched, after O2 plasma ashing, and after wet cleaning for fluorocarbon polymer.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"130 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125439614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Investigation of residual stress effect during the anodic bonding process with different bondable materials for wafer level packaging design","authors":"Xiaodong Hu, Maozhou Meng, Manuel Baeuscher, U. Hansen, S. Maus, O. Gyenge, P. Mackowiak, B. Mukhopadhyay, N. Vokmer, O. Ehrmann, Klaus Dieter Lang, H. Ngo","doi":"10.1109/EPTC.2016.7861498","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861498","url":null,"abstract":"The anodic bonding technology is a well-established industrial technique, which has been reported to account for the mainstream packaging methods in Micro-Electro-Mechanical-Systems (MEMS) devices, such as hermetic sealing, encapsulation, and wafer level packaging. It is widely recognized that the CTEs of many bondable materials are temperature dependent. The residual stress is induced between the bonding interface during the cooling process. This residual stress degrades the device's performance, e.g. its offset, linearity, sensitivity or dynamic behavior. Currently, the mainstream methods for improving anodic bonding performance focus on reducing the bonding temperature, using a thinner glass layer, or using materials with optimized CTE (similar to silicon over a wide temperature range) to reduce the residual stress. As we understand[1], decreasing the bonding temperature reduces the bond quality. In this work, the residual stress is investigated by using the classical lamination theory (CLT) and experiments. The experimental observation showed a good agreement with the CLT calculation method. The study illustrates an efficient methodology to estimate the residual stress in an anodically bonded pair which leads to some suggestions to optimize the design of wafer level packaging.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125582665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Characterization of anodic bondable LTCC for wafer-level packaging","authors":"Xiaodong Hu, Manuel Bäuscher, P. Mackowiak, Yucheng Zhang, O. Hoelck, H. Walter, M. Ihle, S. Ziesche, U. Hansen, S. Maus, O. Gyenge, B. Mukhopadhyay, O. Ehrmann, K. Lang, H. Ngo","doi":"10.1109/EPTC.2016.7861529","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861529","url":null,"abstract":"This work helps to clarify the effects on bondable Low Temperature Cofiered Cofired Ceramic(LTCC) material from Fraunhofer IKTS under different bonding conditions as changes in temperature, voltage and time. The Paper investigates silicon bonded to LTCC and silicon with a thin aluminum layer bonded to LTCC and compares both with anodic bonding of standard Borofloat 33® from Schott GmbH to silicon. The result of this work provides a comprehensive overview of bonding parameters for the materials Borofloat 33® and LTCC. An inspection of the bonding quality is carried out, which includes the optical inspection of the bonded area and interface observation via a scanning electron microscope (SEM). The bonding quality is also shown with the charge transfer during the bonding process. This paper can be used to achieve a higher degree of freedom in the design of hermetic wafer level packaging for various Micro-Electro-Mechanical System(MEMS) devices made of glass and ceramic materials.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129215396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thermomechanical reliability of a Cu-TSV integration model based on 3D fabrication processes","authors":"Yunna Sun, Seung-lo Lee, Yanmei Liu, Jiangbo Luo, Yan Wang, G. Ding, Hong Wang, Jingyuan Yao","doi":"10.1109/EPTC.2016.7861573","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861573","url":null,"abstract":"In the 3D integration stages, the structure of the TSV is changed with the development of the procedure. The 3D though silicon via (TSV) integration models with the new updated structure depended on the integration processes (fabricating redistribution layer (RDL), reflowing solders and filling underfill) were analytically studied in this work. The equivalent stress, von Mises stress, was used to describe and evaluate the change rule and trend of the 3D TSV integration models during the integration integrations. The changing mechanism of thermal stress and strain on the updated models was varied for the free-form deformation space was substituted by the new fabricating structure. The thermal mechanical stability of the updated 3D TSV integration model is analyzed by the steady-state solver finite element method (FEM). The maximal von Mises stress of the updated models decreased with the procedures carried on. The thermal mechanical reliability of final 3D TSV integration model during the operating stage was simulated by the time-dependent solver of FEM. After 3 cycles the maximal thermal stress and strain at the maximal temperature (MT) dropped to near the yield stress of Cu, nevertheless, in the 6 cycles the maximum of the MT raised up but still less than the maximum of the past three cycles may result from the reshaped structure and strain harness processes. The tearing and cracks might be induced for the tensile stress in both X and Y directions are all enlarged greatly. However, the shear stress got into a stable value about 105 MPa after 2 cycles.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"100 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128013920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Evolution of the topographical and chemical signatures of plasma-treated surfaces along the staging time pathway","authors":"I. Arellano, Amor Zapanta","doi":"10.1109/EPTC.2016.7861567","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861567","url":null,"abstract":"Plasma treatment is a widely used process in the semiconductor and electronics industries for surface preparation, via contamination removal and surface activation, promoting interfacial adhesion resulting in improved wire bondability and decreased occurrence of delamination at the interface. Due to the sensitivity of the surface to its immediate environment, the activated surface gradually lose its wettability. Thus, the positive plasma treatment effect diminishes over time, prompting the critical question about the duration wherein the surface is active. In the jargon of assembly process control, this duration is defined as the staging time; the total time from plasma treatment to the completion of the next process step, i.e., wirebond or molding. In this study, we monitor the topographical and chemical evolution of the surface prior to plasma treatment, immediately after plasma treatment, and at certain time points up to 72 h after plasma treatment, with the aim of correlating a measurable parameter such as contact angle (CA) to the topography (roughness) and chemical nature (oxide thickness and functionality) of the surface. Using scanning electron microscopy (SEM) and non-contact atomic force microscopy (NC-AFM), sessile drop contact angle meter, and sequential electro-reduction analysis (SERA), we show that the improvement of wettability imparted by the plasma treatment process arises from the stability of the surface topography (physical) and the promotion of the Cu2O layer (chemical). The loss of surface activation is possibly due to the reduction of the Cu2O layer, resulting from its conversion to CuO.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128558872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Ga-a masking contamination source to prevent FIB cross-section on Al film","authors":"L. Tang, J. Woo, L. Wong","doi":"10.1109/EPTC.2016.7861434","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861434","url":null,"abstract":"Pure Gallium metal is a good adhesive agent which can be used to paste small coupons on full wafer for metal growth in high temperature PVD chamber as Ga has low vapor pressure in high temperature. However, when the process chamber exceeds a certain critical temperature, Gallium at the back of the coupon can contaminate front metal surface in process chamber to form a Ga rich metal surface layer. With such Ga contamination, Ga+ based FIB (Focus Ion Beam) cannot be used to perform cross-section on the metal film has never been reported. We have observed this phenomenon on thick Al film growth on SiO2/Si substrate. In this paper, we described the details of such phenomenon and listed out a possible explanation.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127676250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An accurate calculation method on thermal effectiveness of TSV and wire","authors":"Yudan Pi, Wei Wang, Yufeng Jin","doi":"10.1109/EPTC.2016.7861544","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861544","url":null,"abstract":"With the rapid increment of the power density and decrement of chip size, thermal management has become a critical problem in three-dimensional integrated circuit (3D IC). Through-silicon-via (TSV) is widely used to alleviate thermal problems thanks to its high thermal conductivity. However, thermal effectiveness of TSV in the thermal management varies in different situations. In this paper, based on a simplified thermal resistance calculation of heat dissipation path constructed by TSV and Cu wire, thermal effectiveness of TSV is defined for thermal management. The simplified model is verified by a full scale numerical simulation. The present thermal effectiveness shows potential in engineering guidelines for TSV and Cu wire design in thermal-aware 3D IC floorplanning.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122341934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Determination of dielectric thickness, constant, and loss tangent from cavity resonators","authors":"A. Engin, I. Ndip, K. Lang, J. Aguirre","doi":"10.1109/EPTC.2016.7861533","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861533","url":null,"abstract":"For high-speed digital and high-frequency analog applications, accurate determination of material properties are critical. Technological tolerances on printed circuit boards and packages result in variations of the dielectric thickness, constant, and loss tangent. These properties may also change depending on the process and location on the panel. Hence a methodology is needed where these properties can be measured using test coupons on a panel. Previous research focuses on the determination of dielectric constant and loss tangent using coupons in the form of resonators or transmission lines. However, dielectric thickness also shows significant variation from vendor-supplied values. In this paper, we present a new method that allows to extract the dielectric thickness from resonator measurements as well, hence providing a unique capability for non-destructive monitoring of geometrical as well as electrical properties of printed circuit boards and packages.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127805447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The influence of bond-pad smear crevices on IMC corrosion in Cu-Al bonds","authors":"M. Farrugia","doi":"10.1109/EPTC.2016.7861456","DOIUrl":"https://doi.org/10.1109/EPTC.2016.7861456","url":null,"abstract":"Since the introduction of Cu wire-bonding in the semiconductor industry, corrosion of the Cu-Al intermetallics (IMCs) has been one of the main concerns in developing reliable products using this interconnect technology. Much insight has been gained in selecting suitable bill-of-materials, controlling levels of halides and pH, contamination control and controlling contamination ingress in the package, as well as creating ball bonds with high levels of Intermetallic coverage. But yet it is clear that other, many times unknown, factors also play a role. The work presented here attempts to shed more light on one other suspected factor, the crevice created between the ball bond and the bond-pads deformed splash.","PeriodicalId":136525,"journal":{"name":"2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121551338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}