Molding process development for high density I/Os Fan-Out Wafer Level Package (FOWLP) with fine pitch RDL

Abstract

With the perpetual demand for greater functionalities, better performance and greater energy efficiency at cheaper manufacturing cost and smaller form factor, Fan-Out Wafer Level Packaging (FOWLP) technology has emerged as one of the most promising technology in fulfilling the demands from electronic devices for mobile and network applications. In our FOWLP mold-first approach development work, we developed the 300mm compression molding process for high density input/output (IO)s reconstituted FOWLP mold wafer fabricated with fine pitch redistributed layer (RDL) of line width / line space (LW/LS) ≤5/5μm using the conventional mold-first approach. Our compression molding process development aims to achieve a chip-to-mold non planarity ≤3μm, warpage of reconstituted FOWLP mold wafer ≤1mm and wafer level die shift ≤10μm. In this paper, we will discuss on the 300mm compression molding development work like materials selection, pick-and-place (PnP) process parameters and die shift compensation via constant and dynamic pre-shift methodologies in achieving our targeted specifications for the fabrication of fine pitch RDL FOWLP.