Extremely low warpage coreless substrate for SiP module

Abstract

The system-in-Package (SiP) module market has grown significantly over the past several years and it is now one of the fastest growing packaging technologies in the semiconductor industry driven by lower cost, smaller form factor, higher levels of integration and better performance. In addition, for handheld and mobile application the coreless substrate had been evaluated to replace buildup coded substrate not only thinner thickness but superior electrical performance. However, coreless substrate causes severe package warpage issue due to lack of rigid and low CTE core. In this work, the three Dimensional (3-D) aMA, as a non-contact optical deformation measurement method were carrier to explore and compare strip substrate warpage performance between cored and coreless substrate. To reduce the warpage issue of coreless substrate, the parametric factors on the structure and material would be investigated. These design guides are then studied by finite element modeling to understand mechanism for warpage improvement. From the result, it shows that the strip substrate warpage of coreless is higher 4∼5 times than cored substrate. Besides, the dielectric material property selection is critically factor for warpage control. Furthermore, asymmetric thickness design of cu layer and soldermask layer is another effective for warpage reduction. The bottom layers of Cu and soldermask should be thicker than top layers. A structural design and material property selection guides is then proposed.